sysauend.c

au1500开发的应用程序

/* sysAuEnd.c - system network interface support library for auEnd driver */

/* Copyright 2002-2004 Founder Communications,Inc. */

/*
 * This file has been developed or significantly modified by the
 * MIPS Center of Excellence Dedicated Engineering Staff.
 * This notice is as per the MIPS Center of Excellence Master Partner
 * Agreement, do not remove this notice without checking first with
 * WR/Platforms MIPS Center of Excellence engineering management.
 */

/*
modification history
--------------------
01a,14mar05,fhchen  adapted from pb1500_mips32sf/sysNetif.c (ver 01h)
*/

/*
DESCRIPTION

This is a modified version of WRS-supplied configuration module for
the VxWorks auEnd END driver.

It performs the dynamic parameterization of the auEnd driver.

Both MACs on AU1500 are used. Phy chip is RTL8201BL, phy0's address
is 00001b, phy1's address is 10001b. GPIO203 and GPIO204 are connected to
RESETB of phy0 and phy1 respectively.

*/

/* includes */

#include "vxWorks.h"
#include "taskLib.h"
#include "sysLib.h"
#include "config.h"
#include "stdio.h"
#include "intLib.h"
#include "sysGpio.h"

#ifdef INCLUDE_END
#ifdef INCLUDE_AUEND

#include "auEnd.h"

/* AU INTC Interrupt masks */

#define AU_INTC_MAC0		28           /* MAC 0 int mask offset */
#define AU_INTC_MAC1		29           /* MAC 1 int mask offset */
#define AU_END_USER_FLAGS       0

#ifndef SYS_WB_FLUSH
#define SYS_WB_FLUSH()                          \
    {                                           \
    IMPORT void sysWbFlush (void);              \
    sysWbFlush();                               \
    }
#endif/* SYS_WB_FLUSH */

IMPORT END_TBL_ENTRY    endDevTbl[];         /* end device table */

/*******************************************************************************
*
* sysLanAuInit - prepare LAN adapter for END driver initialization
*
* This routine initializes the load string required by AU END device driver.  It
* also initializes device interrupts and disable them. It is called from
* sysHwInit2().
*
* RETURNS: OK/ERROR
*/

STATUS sysLanAuInit (void)
    {

    /* Load string for AU MAC 0 */

    sprintf (endDevTbl[0].endLoadString,
	     "0x%x:0x%x:0x%x:%d:%d:%d:%d:0x%x",
	     AU_MAC0_REG_BASE,               /* MAC register base        */
	     AU_MAC0_DMA_BASE,               /* MAC DMA register base    */
	     AU_MAC0_ENABLE,                 /* MAC enable register      */
	     IV_MAC0_DMA_VEC,                /* MAC interrupt vector     */
	     AU_INTC_MAC0,                   /* hw interrupt level       */
	     2,                              /* packet load offset       */
	     128,                            /* qty of clusters to alloc */
	     AU_END_USER_FLAGS               /* flags                    */
	     );

    /* Disable MAC0 interrupt */

    AU_INTC_MASK_CLEAR(0)    = (1 << AU_INTC_MAC0);
    SYS_WB_FLUSH();

    /* Level High interrupts */

    AU_INTC_CONFIG2_SET(0)   = (1 << AU_INTC_MAC0);
    AU_INTC_CONFIG1_CLEAR(0) = (1 << AU_INTC_MAC0);
    AU_INTC_CONFIG0_SET(0)   = (1 << AU_INTC_MAC0);
    SYS_WB_FLUSH();

    /* Load string for AU MAC 1 */
    
    sprintf (endDevTbl[1].endLoadString,
	     "0x%x:0x%x:0x%x:%d:%d:%d:%d:0x%x",
	     AU_MAC1_REG_BASE,               /* MAC register base        */
	     AU_MAC1_DMA_BASE,               /* MAC DMA register base    */
	     AU_MAC1_ENABLE,                 /* MAC enable register      */
	     IV_MAC1_DMA_VEC,                /* MAC interrupt vector     */
	     AU_INTC_MAC1,                   /* hw interrupt level       */
	     2,                              /* packet load offset       */
	     128,                            /* qty of clusters to alloc */
	     AU_END_USER_FLAGS               /* flags                    */
	     );

    /* Disable MAC1 interrupt  */
    
    AU_INTC_MASK_CLEAR(0)    = (1 << AU_INTC_MAC1);
    SYS_WB_FLUSH();

    /* Level High interrupts */

    AU_INTC_CONFIG2_SET(0)   = (1 << AU_INTC_MAC1);
    AU_INTC_CONFIG1_CLEAR(0) = (1 << AU_INTC_MAC1);
    AU_INTC_CONFIG0_SET(0)   = (1 << AU_INTC_MAC1);
    SYS_WB_FLUSH();

    return (OK);
    }

/******************************************************************************
*
* sysLanAuIntEnable - enable Au MAC interrupts
*
* This routine enables specified Au MAC interrupts.  This may involve operations
* on interrupt controller. It is required by auEnd driver.
*
* RETURNS: OK or ERROR for invalid arguments.
*/
 
STATUS sysLanAuIntEnable
    (
    int level           /* level number */
    )
    {
    if ((level != AU_INTC_MAC0) && (level != AU_INTC_MAC1))
        return (ERROR);

    /* Set mask bit to enable it */

    AU_INTC_MASK_SET(0) = (1 << level);
    SYS_WB_FLUSH();

    return (OK);
    }
 
/******************************************************************************
*
* sysLanIntDisable - disable au MAC interrupts
*
* This routine disables specified Au MAC interrupts.  This may involve
* operations on interrupt controller. It is required by auEnd driver.
*
* RETURNS: OK or ERROR for invalid arguments.
*/
 
STATUS sysLanAuIntDisable
    (
    int level           /* level number */
    )
    {
    if ((level != AU_INTC_MAC0) && (level != AU_INTC_MAC1))
        return (ERROR);

    /* Clear mask bit to disable it */

    AU_INTC_MASK_CLEAR(0) = (1 << level);
    SYS_WB_FLUSH();

    return (OK);
    }
 
/*******************************************************************************
*
* sysLanAuEnetAddrGet - get Ethernet address
*
* This routine call sysEnetAddrGet to get MAC address and dealing with endian
* issue.
*
* RETURNS: OK or ERROR if could not be obtained.
*/
 
STATUS sysLanAuEnetAddrGet
    (
    AU_DRV_CTRL *  pDrvCtrl,   /* Driver control */
    char *         enetAdrs    /* store returned MAC address */
    )
    {

    UINT8	eAdrs[MAC_ADDRS_SIZE];
    STATUS	status;

    status = sysEnetAddrGet(pDrvCtrl->unit,eAdrs); 

    if (OK == status)
	{

#if (_BYTE_ORDER == _BIG_ENDIAN)
        int i;

        for (i = 0; i < MAC_ADDRS_SIZE; i++) 
            enetAdrs[i] = eAdrs[MAC_ADDRS_SIZE-1-i];
#else
	memcpy(enetAdrs, eAdrs, MAC_ADDRS_SIZE);
#endif  /* _BYTE_ORDER == _BIG_ENDIAN */
        }

    return status;
    }

/*******************************************************************************
*
* sysPhyReset - reset phy chip
*
* This routine reset the specified on board RTL8201BL phy chip using gpio
* routines. For a complete reset function, the RESETB of RTL8201BL must be
* asserted low for at least 10ms.
*
* RETURNS: NONE
*/

void sysPhyReset(int resetPin)
    {
    /* pull reset pin low */

    sysGpioWrite(PHY_RESET_PORT, resetPin, PHY_RESET_LEVEL);

    /* delay 20ms */
    
    DELAY_MS(20);
    
    /* pull reset pin high again */

    sysGpioWrite(PHY_RESET_PORT, resetPin, LOGIC_HIGH);
    
    }

#endif /* INCLUDE_AUEND */
#endif /* INCLUDE_END */