motfccend.c

au1500开发的应用程序

to comply with certain requirements as described in the 802.3u IEEE Standard.
There is not buil-in support in the FCC for the MII management interface.
This means that the clocking on the MDC line and the framing of the information
on the MDIO signal have to be done in software. Hence, this routine is 
expected to read the value from the MDIO line in <bitVal>, while properly 
sourcing the MDC clock to a PHY, for one bit time.

.IP `_func_motFccPhyInit'
.CS
    FUNCPTR _func_motFccPhyInit
.CE
This driver sets the global variable `_func_motFccPhyInit' to the 
MII-compliant media initialization routine miiPhyInit(). If the user 
wishes to exploit a different way to configure the PHY, he may set
this variable to his own media initialization routine, tipically
in sysHwInit().
.IP `_func_motFccHbFail'
.CS
    FUNCPTR _func_motFccHbFail
.CE
The FCC may be configured to perform heartbeat check following end 
of transmission, and to report any failure in the relevant TBD status field. 
If this is the case, and if the global variable `_func_motFccHbFail'
is not NULL, the routine referenced to by `_func_motFccHbFail' is called,
with a pointer to the driver control structure as parameter. Hence,
the user may set this variable to his own heart beat check fail routine,
where he can take any action he sees appropriate.
The default value for the global variable `_func_motFccHbFail' is NULL.

.IP `_func_m82xxDpramFccMalloc'
.CS
    FUNCPTR _func_m82xxDpramFccMalloc
.CE

.IP `_func_m82xxDpramFree'
.CS
    FUNCPTR _func_m82xxDpramFree
.CE

.IP `_func_m82xxDpramFccFree'
.CS
    FUNCPTR _func_m82xxDpramFccFree
.CE

The FCC can be configured to utilize the dual ported ram located in
the MPPC8260 CMP. In this case the user flag MOT_FCC_USR_DPRAM_ALOC is set 
and the global variables _func_m82xxDpramFccMalloc, _func_m82xxDpramFree, and 
_func_m82xxDpramFccFree must be populated by the BSP with the FUNCPTRs to 
m82xxDpramFccMalloc(),  m82xxDpramFree(), and m82xxDpramFccFree() (respectively)
from m82xxDpramLib.h. These functions are then used by the motFccEnd driver to 
allocate and free memory in the dual ported ram. If any of these FUNCPTRs 
are left NULL the motFccPramInit() will return an ERROR and the motFccEnd
driver will not initialize.     

.LP

SYSTEM RESOURCE USAGE
If the driver allocates the memory for the BDs to share with the FCC,
it does so by calling the cacheDmaMalloc() routine.  For the default case
of 64 transmit buffers and 32 receive buffers, the total size requested 
is 776 bytes, and this includes the 8-byte alignment requirement of the 
device.  If a non-cacheable memory region is provided by the user, the 
size of this region should be this amount, unless the user has specified 
a different number of transmit or receive BDs. 

This driver can operate only if this memory region is non-cacheable
or if the hardware implements bus snooping.  The driver cannot maintain
cache coherency for the device because the BDs are asynchronously
modified by both the driver and the device, and these fields share 
the same cache line.

If the driver allocates the memory for the data buffers to share with the FCC,
it does so by calling the memalign () routine.  The driver does not need to
use cache-safe memory for data buffers, since the host CPU and the device are
not allowed to modify buffers asynchronously. The related cache lines
are flushed or invalidated as appropriate. For the default case
of 7 transmit clusters and 32 receive clusters, the total size requested 
for this memory region is 112751 bytes, and this includes the 32-byte 
alignment and the 32-byte pad-out area per buffer of the device.  If a 
non-cacheable memory region is provided by the user, the size of this region 
should be this amount, unless the user has specified a different number 
of transmit or receive BDs. 

TUNING HINTS

The only adjustable parameters are the number of TBDs and RBDs that will be
created at run-time.  These parameters are given to the driver when 
motFccEndLoad() is called.  There is one RBD associated with each received 
frame whereas a single transmit packet normally uses more than one TBD.  For 
memory-limited applications, decreasing the number of RBDs may be 
desirable.  Decreasing the number of TBDs below a certain point will 
provide substantial performance degradation, and is not reccomended. An 
adequate number of loaning buffers are also pre-allocated to provide more 
buffering before packets are dropped, but this is not configurable.

The relative priority of the netTask and of the other tasks in the system
may heavily affect performance of this driver. Usually the best performance 
is achieved when the netTask priority equals that of the other 
applications using the driver.

SPECIAL CONSIDERATIONS

SEE ALSO: ifLib,
.I "MPC8260 Fast Ethernet Controller (Supplement to the MPC860 User's Manual)"
.I "Motorola MPC860 User's Manual",

INTERNAL
This driver contains conditional compilation switch MOT_FCC_DBG.
If defined, adds debug output routines.  Output is further
selectable at run-time via the motFccEndDbg global variable.
*/

#include "vxWorks.h"
#include "wdLib.h"
#include "iv.h"
#include "vme.h"
#include "net/mbuf.h"
#include "net/unixLib.h"
#include "net/protosw.h"
#include "sys/socket.h"
#include "sys/ioctl.h"
#include "errnoLib.h"
#include "errno.h"
#include "memLib.h"
#include "intLib.h"
#include "net/route.h"
#include "iosLib.h"
#include "errnoLib.h"
#include "vxLib.h"
#include "cacheLib.h"
#include "logLib.h"
#include "netLib.h"
#include "stdio.h"
#include "stdlib.h"
#include "sysLib.h"
#include "taskLib.h"

#include "net/systm.h"
#include "sys/times.h"
#include "net/if_subr.h"

#undef ETHER_MAP_IP_MULTICAST
#include "etherMultiLib.h"
#include "end.h"
#include "semLib.h"

#define    END_MACROS
#include "endLib.h"
#include "lstLib.h"
#include "miiLib.h"

#include "m8260IntrCtl.h"
#include "drv/sio/m8260Cp.h"
#include "drv/sio/m8260CpmMux.h"
#include "drv/end/motFccEnd.h"

/* defines */

/* Driver debug control */

/* for debugging */

#ifdef MOT_FCC_DBG 
# undef MOT_FCC_DBG 
#endif

/* debug, temp */
#if 0
#define MOT_FCC_DBG
#define MOT_FCC_DBG_ALL
#endif

/* Driver debug control */

#ifdef MOT_FCC_DBG
#define MOT_FCC_DBG_OFF		0x0000
#define MOT_FCC_DBG_RX		0x0001
#define MOT_FCC_DBG_TX		0x0002
#define MOT_FCC_DBG_POLL	0x0004
#define MOT_FCC_DBG_MII		0x0008
#define MOT_FCC_DBG_LOAD	0x0010
#define MOT_FCC_DBG_IOCTL	0x0020
#define MOT_FCC_DBG_INT		0x0040
#define MOT_FCC_DBG_START	0x0080
#define MOT_FCC_DBG_INT_RX_ERR	0x0100
#define MOT_FCC_DBG_INT_TX_ERR	0x0200
#define MOT_FCC_DBG_ANY		0xffff

#ifdef MOT_FCC_DBG_ALL
 UINT32	motFccEndDbg = MOT_FCC_DBG_ANY;
#else
 UINT32	motFccEndDbg = MOT_FCC_DBG_INT_RX_ERR|MOT_FCC_DBG_INT_TX_ERR;
#endif

UINT32	motFccRxBsyErr = 0x0;
UINT32	motFccTxErr = 0x0;
UINT32	motFccHbFailErr = 0x0;
UINT32	motFccTxLcErr = 0x0;
UINT32	motFccTxUrErr = 0x0;
UINT32	motFccTxCslErr = 0x0;
UINT32	motFccTxRlErr = 0x0;
UINT32	motFccRxLgErr = 0x0;
UINT32	motFccRxNoErr = 0x0;
UINT32	motFccRxCrcErr = 0x0;
UINT32	motFccRxOvErr = 0x0;
UINT32  motFccRxShErr = 0x0;
UINT32  motFccRxLcErr = 0x0;
UINT32  motFccRxMemErr = 0x0;

DRV_CTRL *  pDrvCtrlDbg = NULL;

#define MOT_FCC_HB_FAIL_ADD	motFccHbFailErr++;
#define MOT_FCC_RX_LG_ADD	motFccRxLgErr++;
#define MOT_FCC_RX_NO_ADD	motFccRxNoErr++;
#define MOT_FCC_RX_CRC_ADD	motFccRxCrcErr++;
#define MOT_FCC_RX_OV_ADD	motFccRxOvErr++;
#define MOT_FCC_RX_LC_ADD	motFccRxLcErr++;
#define MOT_FCC_RX_SH_ADD	motFccRxShErr++;
#define MOT_FCC_RX_MEM_ADD(p) (p)->Stats->motFccRxMemErr++;

#define MOT_FCC_LOG(FLG, X0, X1, X2, X3, X4, X5, X6)			\
    {									\
    if (motFccEndDbg & FLG)						\
        logMsg (X0, X1, X2, X3, X4, X5, X6);			        \
    }

#else /* MOT_FCC_DBG */

#define MOT_FCC_HB_FAIL_ADD
#define MOT_FCC_RX_MEM_ADD(p)
#define MOT_FCC_LOG(FLG, X0, X1, X2, X3, X4, X5, X6)

#endif /* MOT_FCC_DBG */

/* general macros for reading/writing from/to specified locations */

/* Cache and virtual/physical memory related macros */

#define MOT_FCC_PHYS_TO_VIRT(physAddr)					    \
	CACHE_DRV_PHYS_TO_VIRT (&pDrvCtrl->bdCacheFuncs, (char *)(physAddr))

#define MOT_FCC_VIRT_TO_PHYS(virtAddr)					    \
	CACHE_DRV_VIRT_TO_PHYS (&pDrvCtrl->bdCacheFuncs, (char *)(virtAddr))

#define MOT_FCC_BD_CACHE_INVAL(address, len)			    	    \
        CACHE_DRV_INVALIDATE (&pDrvCtrl->bdCacheFuncs, (address), (len))

#define MOT_FCC_CACHE_INVAL(address, len)                                   \
	CACHE_DRV_INVALIDATE (&pDrvCtrl->bufCacheFuncs, (address), (len))

#define MOT_FCC_CACHE_FLUSH(address, len)                                   \
	CACHE_DRV_FLUSH (&pDrvCtrl->bufCacheFuncs, (address), (len))

/* driver flags */

#define MOT_FCC_OWN_BUF_MEM	0x01	/* internally provided memory for data*/
#define MOT_FCC_INV_TBD_NUM	0x02	/* invalid tbdNum provided */
#define MOT_FCC_INV_RBD_NUM	0x04	/* invalid rbdNum provided */
#define MOT_FCC_POLLING		0x08	/* polling mode */
#define MOT_FCC_PROM		0x20    /* promiscuous mode */
#define MOT_FCC_MCAST		0x40    /* multicast addressing mode */
#define MOT_FCC_FD		0x80    /* full duplex mode */
#define MOT_FCC_OWN_BD_MEM	0x10	/* internally provided memory for BDs */

/* shortcuts */

#define MOT_FCC_FLAG_CLEAR(clearBits)					\
    (pDrvCtrl->flags &= ~(clearBits))

#define MOT_FCC_FLAG_SET(setBits)					\
    (pDrvCtrl->flags |= (setBits))

#define MOT_FCC_FLAG_GET()						\
    (pDrvCtrl->flags)

#define MOT_FCC_FLAG_ISSET(setBits)					\
    (pDrvCtrl->flags & (setBits))

#define MOT_FCC_PHY_FLAGS_SET(setBits)					\
    (pDrvCtrl->phyInfo->phyFlags |= (setBits))

#define MOT_FCC_PHY_FLAGS_ISSET(setBits)				\
    (pDrvCtrl->phyInfo->phyFlags & (setBits))

#define MOT_FCC_PHY_FLAGS_GET(setBits)					\
    (pDrvCtrl->phyInfo->phyFlags)

#define MOT_FCC_PHY_FLAGS_CLEAR(clearBits)				\
    (pDrvCtrl->phyInfo->phyFlags &= ~(clearBits))

#define MOT_FCC_USR_FLAG_ISSET(setBits)					\
    (pDrvCtrl->userFlags & (setBits))

#define END_FLAGS_ISSET(setBits)					\
    ((&pDrvCtrl->endObj)->flags & (setBits))

#define MOT_FCC_ADDR_GET(pEnd)                                          \
    ((pEnd)->mib2Tbl.ifPhysAddress.phyAddress)

#define MOT_FCC_ADDR_LEN_GET(pEnd)                                      \
    ((pEnd)->mib2Tbl.ifPhysAddress.addrLength)

/* some BDs definitions */

/* 
 * the total is 0x630 and it accounts for the required alignment
 * of receive data buffers, and the cluster overhead.
 */

#define XXX_FCC_MAX_CL_LEN      ((MII_ETH_MAX_PCK_SZ			\
				 + (MOT_FCC_BUF_ALIGN - 1)		\
				 + MOT_FCC_BUF_ALIGN			\
				 + (CL_OVERHEAD - 1))			\
				 & (~ (CL_OVERHEAD - 1)))

#define MOT_FCC_MAX_CL_LEN      ROUND_UP(XXX_FCC_MAX_CL_LEN,MOT_FCC_BUF_ALIGN)

#define MOT_FCC_RX_CL_SZ       (MOT_FCC_MAX_CL_LEN)
#define MOT_FCC_TX_CL_SZ       (MOT_FCC_MAX_CL_LEN)

/* read/write macros to access internal memory */

#define MOT_FCC_REG_LONG_WR(regAddr, regVal)				\
    {									\
    UINT32 temp = 0;							\
									\
    temp = (UINT32) MOT_FCC_VIRT_TO_PHYS (regAddr);			\
									\
    MOT_FCC_LONG_WR ((UINT32 *) (temp), (regVal));			\
    }									

#define MOT_FCC_REG_LONG_RD(regAddr, regVal)				\
    {									\
    UINT32 temp = 0;							\
									\
    temp = (UINT32) MOT_FCC_VIRT_TO_PHYS (regAddr);			\
									\
    MOT_FCC_LONG_RD ((UINT32 *) (temp), (regVal));			\
    }									

#define MOT_FCC_REG_WORD_WR(regAddr, regVal)				\
    {									\
    UINT32 temp = 0;							\
									\
    temp = (UINT32) MOT_FCC_VIRT_TO_PHYS (regAddr);			\
									\
    MOT_FCC_WORD_WR ((UINT16 *) (temp), (regVal));			\
    }									

#define MOT_FCC_REG_WORD_RD(regAddr, regVal)				\
    {									\
    UINT32 temp = 0;							\
									\
    temp = (UINT32) MOT_FCC_VIRT_TO_PHYS (regAddr);			\
									\
    MOT_FCC_WORD_RD ((UINT16 *) (temp), (regVal));			\
    }									

/* macros to read/write tx/rx buffer descriptors */

#define MOT_FCC_BD_WORD_WR(bdAddr, bdOff, bdVal)			\
    {									\
    UINT32 temp = 0;							\
									\
    temp = (UINT32) MOT_FCC_VIRT_TO_PHYS ((bdAddr) + (bdOff));		\
									\