📄 sysmotfccend.c
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* a 60x bus address for BDS. In these cases do not set the LBUS
* flag.
*/
motFccBufsDescSize = MOT_FCC3_BDS_SIZE;
if ((motFccBufsDescAdr = (UINT32)m82xxDpramAlignedMalloc (MOT_FCC3_BDS_SIZE,8)) == 0)
{
motFccBufsDescAdr = -1UL;
}
/*
* On the second pass through here, we actually create
* the initialization parameter string on the fly.
* Note that we will be handed our unit number on the
* second pass and we need to preserve that information.
* So we use the unit number handed from the input string.
*/
pStr = strcpy (paramStr, pParamStr);
/* Now, we get to the end of the string */
pStr += strlen (paramStr);
/* finish off the initialization parameter string */
sprintf (pStr, motFccEndParamTemplate,
(UINT) vxImmrGet(),
MOT_FCC3_NUM,
motFccBufsDescAdr,
motFccBufsDescSize,
motFccBufsAdr,
motFccBufsSize,
-1UL,-1UL,
MOT_FCC3_TBD_NUM,
MOT_FCC3_RBD_NUM,
MOT_FCC3_PHY_ADDR,
MOT_FCC3_DEF_PHY_MODE,
&motFccAnOrderTbl,
motFccFlags,
MOT_FCC3_MBLK_RBD_RATIO,
MOT_FCC3_CLUS_RBD_RATIO
);
if ((pEnd = (END_OBJ *) motFccEndLoad(paramStr)) == (END_OBJ *)NULL)
{
logMsg ("sysMotFcc3Endload: Error, motFccEndLoad failed to load driver for FCC3\n",
0, 0, 0, 0, 0, 0);
}
}
return pEnd;
}
/***********************************************************************
*
* sysMiiPhyDuplex - check if link is Full Duplex
*
* This routine check if the link is Full Duplex or not. In RTL8201BL,
* bit 8 of reg 0 reflect the duplex status.
*
* RETURNS: 1 if Ful Duplex or 0 if not.
*/
LOCAL STATUS sysMiiPhyDuplex
(
PHY_INFO * pPhyInfo,
int * pDuplex
)
{
UINT16 miiStat;
int retVal;
MII_READ(pPhyInfo->phyAddr, 0, &miiStat, retVal);
if (retVal == OK)
{
*pDuplex = (miiStat & 0x200) ? 1 : 0;
}
return retVal;
}
#if 0
/***********************************************************************
*
* sysMiiInt - MII interrupt service routine
*
* This routine check if the link up or down and update a flag
*
* NOTE:
* - RTL8201BL can not generate interrupt when link is up, this
* function is here just for reference.
*
* RETURNS: None.
*/
LOCAL void sysMiiInt
(
PHY_INFO * pPhyInfo
)
{
UINT16 miiIntStatusReg;
int tmp;
/*
* Clear MII interrupt by reading Int status reg
* Change register 19 to your own value.
*/
MII_READ(pPhyInfo->phyAddr, 19, &miiIntStatusReg, tmp);
++miiNumLinkChgInts;
if (_func_motFccPhyLSCInt)
{
(* _func_motFccPhyLSCInt)(pPhyInfo->pDrvCtrl);
}
}
#endif
/***********************************************************************
*
* sysMiiPhyInit - initialize and configure the PHY devices
*
* This routine scans, initializes and configures the PHY device.
*
* NOTE:
* - RTL8201BL can not generate interrupt when link is up, comment out
* related code.
*
* RETURNS: OK, or ERROR.
*/
LOCAL STATUS sysMiiPhyInit
(
PHY_INFO * pPhyInfo
)
{
int retVal;
#if 0
int tmp;
UINT16 miiIntEnableReg;
#endif
retVal = miiPhyInit (pPhyInfo);
#if 0
if (retVal == OK)
{
MII_READ(pPhyInfo->phyAddr, 18, &miiIntEnableReg, tmp);
if (tmp == OK)
{
intConnect (INUM_TO_IVEC(INUM_IRQ6), sysMiiInt, (int)pPhyInfo);
miiIntEnableReg = 0x12;
MII_WRITE(pPhyInfo->phyAddr, 18, miiIntEnableReg, tmp);
if (tmp == OK)
{
intEnable (INUM_IRQ6);
}
}
}
#endif
return retVal;
}
/***********************************************************************
*
* sysFccEnetEnable - enable the MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required to
* enable the Ethernet device and to connect the MII interface to the FCC.
*
* NOTE:
* - Pins are configured in sysGpioInit in SCB board. Should re-configure
* them here.
*
* RETURNS: OK, or ERROR if the FCC controller cannot be enabled.
*/
STATUS sysFccEnetEnable
(
UINT32 immrVal, /* base address of the on-chip RAM */
UINT8 fccNum /* FCC being used */
)
{
int intLevel;
intLevel = intLock();
if(MOT_FCC1_NUM == fccNum)
{
/* configure pins for FCC1 */
/* PC20: CLK12, PC21: CLK11 */
*M8260_IOP_PCPAR(immrVal) |= (PC21 | PC20);
*M8260_IOP_PCSO(immrVal) &= ~(PC21 | PC20);
*M8260_IOP_PCDIR(immrVal) &= ~(PC21 | PC20);
/* PA14 ~ 21, 26 ~ 28, 30 ~ 31 */
*M8260_IOP_PAPAR(immrVal) |= (PA31 | PA30 | PA28 | PA27 | PA26 |
PA21 | PA20 | PA19 | PA18 | PA17 |
PA16 | PA15 | PA14);
/* set, output */
*M8260_IOP_PADIR(immrVal) |= (PA28 | PA21 | PA20 | PA19 | PA18);
/* clear, input */
*M8260_IOP_PADIR(immrVal) &= ~(PA31 | PA30 | PA27 | PA26 | PA17 |
PA16 | PA15 | PA14);
/* set, special option 1 */
*M8260_IOP_PASO(immrVal) |= (PA31 | PA30 | PA28 | PA27 | PA26);
/* clear, special option 0 */
*M8260_IOP_PASO(immrVal) &= ~(PA21 | PA20 | PA19 | PA18 | PA17 |
PA16 | PA15 | PA14);
/* clock: NMSI, Rx - CLK11, Tx - CLK12, BE CAREFUL, DOUBLE CHECK IT */
*M8260_CMXFCR(immrVal) |= (0x37000000);
}
if(MOT_FCC3_NUM == fccNum)
{
/* configure pins for FCC3 */
/* PC17: CLK15, PC16: CLK16 */
*M8260_IOP_PCPAR(immrVal) |= (PC16 | PC17);
*M8260_IOP_PCSO(immrVal) &= ~(PC16 | PC17);
*M8260_IOP_PCDIR(immrVal) &= ~(PC16 | PC17);
/* PB17 ~ 4, except PB15 */
*M8260_IOP_PBPAR(immrVal) |= (PB17 | PB16 | PB14 | PB13 | PB12 |
PB11 | PB10 | PB9 | PB8 | PB7 |
PB6 | PB5 | PB4);
/* set, output */
*M8260_IOP_PBDIR(immrVal) |= (PB14 | PB7 | PB6 | PB5 | PB4);
/* clear, input */
*M8260_IOP_PBDIR(immrVal) &= ~(PB17 | PB16 | PB13 | PB12 | PB11 |
PB10 | PB9 | PB8);
/* clear, special option 0 */
*M8260_IOP_PBSO(immrVal) &= ~(PB17 | PB16 | PB14 | PB13 | PB12 |
PB11 | PB10 | PB9 | PB8 | PB7 |
PB6 | PB5 | PB4);
/* clock: NMSI, Rx - CLK15, Tx - CLK16 */
*M8260_CMXFCR(immrVal) |= (0x00003700);
}
intUnlock(intLevel);
taskDelay(sysClkRateGet() >> 2);
_func_motFccPhyInit = (FUNCPTR) sysMiiPhyInit;
_func_motFccPhyDuplex = (FUNCPTR) sysMiiPhyDuplex;
return(OK);
}
/***********************************************************************
*
* sysFccEnetDisable - disable MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to disable the Ethernet device and the MII interface to the FCC
* controller. This involves restoring the default values for all the Port
* B and C signals.
*
* RETURNS: OK, always.
*/
STATUS sysFccEnetDisable
(
UINT32 immrVal, /* base address of the on-chip RAM */
UINT8 fccNum /* FCC being used */
)
{
int intLevel;
intLevel = intLock();
if(MOT_FCC1_NUM == fccNum)
{
/* restore FCC3 pins previously set */
*M8260_IOP_PCPAR(immrVal) &= ~(PC21 | PC20);
*M8260_IOP_PAPAR(immrVal) &= ~(PA31 | PA30 | PA28 | PA27 | PA26 |
PA21 | PA20 | PA19 | PA18 | PA17 |
PA16 | PA15 | PA14);
*M8260_IOP_PADIR(immrVal) &= ~(PA28 | PA21 | PA20 | PA19 | PA18);
*M8260_IOP_PASO(immrVal) &= ~(PA31 | PA30 | PA28 | PA27 | PA26);
}
if(MOT_FCC3_NUM == fccNum)
{
/* restore FCC3 pins previously set */
*M8260_IOP_PCPAR(immrVal) &= ~(PC16 | PC17);
*M8260_IOP_PBPAR(immrVal) &= ~(PB17 | PB16 | PB14 | PB13 | PB12 |
PB11 | PB10 | PB9 | PB8 | PB7 |
PB6 | PB5 | PB4);
*M8260_IOP_PBDIR(immrVal) &= ~(PB14 | PB7 | PB6 | PB5 | PB4);
}
/* Disable the interrupt */
intDisable(INUM_FCC1 + fccNum - 1);
intUnlock(intLevel);
return(OK);
}
/***********************************************************************
*
* sysFccEnetAddrGet - get the hardware Ethernet address
*
* This routine provides the six byte Ethernet hardware address that will be
* used by each individual FCC device unit. This routine must copy
* the six byte address to the space provided by <addr>.
*
* RETURNS: OK, or ERROR if the Ethernet address cannot be returned.
*/
STATUS sysFccEnetAddrGet
(
int unit,
UCHAR * pAddr
)
{
/* need extra room for a 'EOS' -- driver may not provide it */
UINT8 eAdrs[MAC_ADRS_LEN + 2];
STATUS status;
status = sysEnetAddrGet(unit,eAdrs);
if (status == OK)
{
memcpy(pAddr, eAdrs, MAC_ADRS_LEN);
}
return status;
}
/***********************************************************************
*
* sysFccEnetCommand - issue a command to the Ethernet interface controller
*
* RETURNS: OK, or ERROR if the Ethernet controller could not be restarted.
*/
STATUS sysFccEnetCommand
(
UINT32 immrVal, /* base address of the on-chip RAM */
UINT8 fccNum, /* FCC being used */
UINT16 command
)
{
return (OK);
}
/***********************************************************************
*
* sysFccMiiBitWr - write one bit to the MII interface
*
* This routine writes the value in <bitVal> to the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
* If <bitVal> is NONE, then the MDIO pin should be left in high-impedance
* state.
*
* SEE ALSO: sysFccMiiBitRd()
*
* RETURNS: OK, or ERROR.
*/
STATUS sysFccMiiBitWr
(
UINT32 immrVal, /* base address of the on-chip RAM */
UINT8 fccNum, /* FCC being used */
INT32 bitVal /* the bit being written */
)
{
miiBitWrCount++;
/*
* we create the timing reference for transfer of info on the MDIO line
* MDIO is mapped on PC9, MDC on PC10. We need to keep the same data
* on MDIO for at least 400 nsec.
*/
*M8260_IOP_PCPAR(immrVal) &= ~(PC10 | PC9);
*M8260_IOP_PCDIR(immrVal) |= (PC10 | PC9);
*M8260_IOP_PCDAT(immrVal) |= (PC10);
switch (bitVal)
{
case 0:
*M8260_IOP_PCDAT(immrVal) &= ~(PC9);
break;
case 1:
*M8260_IOP_PCDAT(immrVal) |= (PC9);
break;
case ((INT32) NONE):
/* put it in high-impedance state */
*M8260_IOP_PCDIR(immrVal) &= ~(PC9);
break;
default:
return (ERROR);
}
/* delay about 200 nsec. */
NSDELAY (200);
/* now we toggle the clock and delay again */
*M8260_IOP_PCDAT(immrVal) &= ~(PC10);
NSDELAY (200);
return (OK);
}
/***********************************************************************
*
* sysFccMiiBitRd - read one bit from the MII interface
*
* This routine reads one bit from the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
*
* SEE ALSO: sysFccMiiBitWr()
*
* RETURNS: OK, or ERROR.
*/
STATUS sysFccMiiBitRd
(
UINT32 immrVal, /* base address of the on-chip RAM */
UINT8 fccNum, /* FCC being used */
INT8 * bitVal /* the bit being read */
)
{
miiBitRdCount++;
/*
* we create the timing reference for transfer of info on the MDIO line
* MDIO is mapped on PC9, MDC on PC10. We can read data on MDIO after
* at least 400 nsec.
*/
*M8260_IOP_PCPAR(immrVal) &= ~(PC10 | PC9);
*M8260_IOP_PCDIR(immrVal) &= ~(PC9);
*M8260_IOP_PCDIR(immrVal) |= (PC10);
*M8260_IOP_PCDAT(immrVal) |= (PC10);
/* delay about 200 nsec. */
NSDELAY (200);
/* now we toggle the clock and delay again */
*M8260_IOP_PCDAT(immrVal) &= ~(PC10);
NSDELAY (200);
/* we can now read the MDIO data on PC9 */
*bitVal = (*M8260_IOP_PCDAT(immrVal) & (PC9)) >> 22;
return (OK);
}
#endif /* INCLUDE_MOTFCCEND */
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