📄 rominit.s
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lis r5, HIADJ(0x00000000) /* read only ? */
addi r5, r5, LO(0x00000000)
stw r5, INIT_PDTEA(r4)
li r5, 0x00
stb r5, INIT_PDTEM(r4)
lis r5, HIADJ(0x00000000) /* read only ? */
addi r5, r5, LO(0x00000000)
stw r5, INIT_LDTEA(r4)
li r5, 0x00
stb r5, INIT_LDTEM(r4)
bclr 20, 0
FUNC_END(romSiuInit)
/******************************************************************************
*
* romMemcInit - initialize the memory controller and SDRAM.
*
* RETURNS: N/A.
*/
FUNC_BEGIN(romMemcInit)
mfspr r30, LR /* save return address */
/* initialize chip selects */
bl romChipSelectInit
/* <MAR>: memory address register, for UPM, not used */
lis r5, HIADJ(0x00000200) /* wrSbc8260Atm: 0x00000200 */
addi r5, r5, LO(0x00000200)
stw r5, INIT_MAR(r4)
/* UPM A,B,C mode registers, not used, set them to 0 */
lis r5, HIADJ(0x00000000)
addi r5, r5, LO(0x00000000)
stw r5, INIT_MAMR(r4)
lis r5, HIADJ(0x00000000)
addi r5, r5, LO(0x00000000)
stw r5, INIT_MBMR(r4)
lis r5, HIADJ(0x00000000)
addi r5, r5, LO(0x00000000)
stw r5, INIT_MCMR(r4)
/*
* <MPTPR>
* Memory Refresh Timer Prescaler Register
* PTR(bit0~7): divide the system clock to get memory
* refresh timers input clock
*/
li r5, 0x1800 /* wrSbc8260Atm: 0x3200 */
sth r5, INIT_MPTPR(r4)
/* <MDR>: memory data register, for UPM, not used */
lis r5, HIADJ(0x00000000)
addi r5, r5, LO(0x00000000)
stw r5, INIT_MDR(r4)
#if FALSE
/*
* <PSDMR>
* 60x SDRAM mode register
* value provide by HW dept. later init in memcSdram60xBusInit
*/
lis r5, HIADJ(0x00000000) /* wrSbc8260Atm: 0x00000000 */
addi r5, r5, LO(0x00000000) /* V100R001SCB: 0xC34E24A6 */
stw r5, INIT_PSDMR(r4)
/*
* <LSDMR>
* local SDRAM mode register
* value provided by HW dept. later init in memcSdramLocalBusInit
*/
lis r5, HIADJ(0x00000000) /* wrSbc8260Atm: 0x00000000 */
addi r5, r5, LO(0x00000000) /* V100R001SCB: 0x416A2566 */
stw r5, INIT_LSDMR(r4)
#endif
/* <PURT>: 60x assigned UPM refresh timer register, not used */
li r5, 0x08
stb r5, INIT_PURT(r4) /* wrSbc8260Atm: 0x08 */
/* <PSRT>: 60x assigned SDRAM refresh timer register */
li r5, 0x27
stb r5, INIT_PSRT(r4) /* wrSbc8260Atm: 0x0E */
/* <LURT>: local assigned UPM refresh timer register, not used */
li r5, 0x0E
stb r5, INIT_LURT(r4) /* wrSbc8260Atm: 0x0E */
/* <LSRT>: local assigned SDRAM refresh timer register */
li r5, 0x27
stb r5, INIT_LSRT(r4) /* wrSbc8260Atm: 0x0E */
#if FALSE
/* no pci bridge on mpc8260, so comment it out */
lis r5, HIADJ(0x00000000)
addi r5, r5, LO(0x00000000)
stw r5, INIT_PCIBR0(r4)
lis r5, HIADJ(0x00000000)
addi r5, r5, LO(0x00000000)
stw r5, INIT_PCIBR1(r4)
lis r5, HIADJ(0x00000000)
addi r5, r5, LO(0x00000000)
stw r5, INIT_PCIMSK0(r4)
lis r5, HIADJ(0x00000000)
addi r5, r5, LO(0x00000000)
stw r5, INIT_PCIMSK1(r4)
#endif
/*
* <RMR>
* reset mode register
* CSRE(bit31):
* - 1: reset generated when core enter MC state
* - 0: reset not generated ...
*/
li r5, 0x0000
sth r5, INIT_RMR(r4)
bl memcSdram60xBusInit
bl memcSdramLocalBusInit
mtspr LR, r30
bclr 20, 0
FUNC_END(romMemcInit)
/******************************************************************************
*
* romChipSelectInit - initialize the chip select
*
* RETURNS: N/A.
*/
FUNC_BEGIN(romChipSelectInit)
mfspr r29, LR /* save LR, r30 used by romMemcInit */
/*---------------------------------------------------------
* CS0: 512KB, 8-bit socket Flash (AM29LV040)
* BR0: FFF00000-FFF7FFFF, MS is GPCM - 60x bus(000)
* OR0: 5 clock cycles wait states
*--------------------------------------------------------*/
lis r5, HIADJ(0xFE000836) /* 0xFFF00C56 */
addi r5, r5, LO(0xFE000836)
stw r5, INIT_OR0(r4)
lis r5, HIADJ(0xFE000801) /* 0xFFF00801 */
addi r5, r5, LO(0xFE000801)
stw r5, INIT_BR0(r4)
/*---------------------------------------------------------
* CS1: 16MB, 16-bit on board Flash (28F128J3)
* BR1: 10000000-10FFFFFF, MS is GPCM - 60x bus(000)
* OR1: 5 clock cycles wait states
*--------------------------------------------------------*/
lis r5, HIADJ(0xFF000C56)
addi r5, r5, LO(0xFF000C56)
stw r5, INIT_OR1(r4)
lis r5, HIADJ(0x10001001)
addi r5, r5, LO(0x10001001)
stw r5, INIT_BR1(r4)
/*---------------------------------------------------------
* CS2: 16MB, 16-bit on board Flash (28F128J3)
* BR2: 11000000-11FFFFFF, MS is GPCM - 60x bus(000)
* OR2: 5 clock cycles wait states
*--------------------------------------------------------*/
lis r5, HIADJ(0xFF000C56)
addi r5, r5, LO(0xFF000C56)
stw r5, INIT_OR2(r4)
lis r5, HIADJ(0x11001001)
addi r5, r5, LO(0x11001001)
stw r5, INIT_BR2(r4)
/*---------------------------------------------------------
* CS3: 64MB, 64-bit SDRAM (MT48LC8M32B * 2)
* BR3: 00000000-03FFFFFF, MS is SDRAM - 60x bus(010)
* OR3: 5 clock cycles wait states
*--------------------------------------------------------*/
lis r5, HIADJ(0xFC002CD0)
addi r5, r5, LO(0xFC002CD0)
stw r5, INIT_OR3(r4)
lis r5, HIADJ(0x00000041)
addi r5, r5, LO(0x00000041)
stw r5, INIT_BR3(r4)
/*---------------------------------------------------------
* CS4: 64MB, 64-bit SDRAM (MT48LC8M32B * 2)
* BR4: 04000000-07FFFFFF, MS is SDRAM - 60x bus(010)
* OR4: 5 clock cycles wait states
*--------------------------------------------------------*/
lis r5, HIADJ(0xFC002CD0)
addi r5, r5, LO(0xFC002CD0)
stw r5, INIT_OR4(r4)
lis r5, HIADJ(0x04000041)
addi r5, r5, LO(0x04000041)
stw r5, INIT_BR4(r4)
/*---------------------------------------------------------
* CS5: 32MB, 32-bit SDRAM (MT48LC8M32B)
* BR5: 20000000-21FFFFFF, MS is SDRAM - local bus(011)
* OR5: 5 clock cycles wait states
*--------------------------------------------------------*/
lis r5, HIADJ(0xFE002CD0)
addi r5, r5, LO(0xFE002CD0)
stw r5, INIT_OR5(r4)
lis r5, HIADJ(0x20001861)
addi r5, r5, LO(0x20001861)
stw r5, INIT_BR5(r4)
/*---------------------------------------------------------
* CS6: 4KB, 8-bit CPLD (device: unkown)
* BR6: 30000000-30000FFF, MS is GPCM - 60x bus(000)
* OR6: 5 clock cycles wait states
*--------------------------------------------------------*/
lis r5, HIADJ(0xFFFF8C56)
addi r5, r5, LO(0xFFFF8C56)
stw r5, INIT_OR6(r4)
lis r5, HIADJ(0x30000801)
addi r5, r5, LO(0x30000801)
stw r5, INIT_BR6(r4)
/*---------------------------------------------------------
* CS9: 64KB, 16 bit FPGA (device: unkown)
* BR9: 40000000-4000FFFF, MS is GPCM - 60x bus(000)
* OR9: 5 clock cycles wait states
*--------------------------------------------------------*/
lis r5, HIADJ(0xFFFF0C56)
addi r5, r5, LO(0xFFFF0C56)
stw r5, INIT_OR9(r4)
lis r5, HIADJ(0x40001001)
addi r5, r5, LO(0x40001001)
stw r5, INIT_BR9(r4)
/*---------------------------------------------------------
* CS7, CS8, CS10, CS11: disabled
*--------------------------------------------------------*/
lis r5, HIADJ(0x00000000)
addi r5, r5, LO(0x00000000)
stw r5, INIT_OR7(r4)
stw r5, INIT_BR7(r4)
stw r5, INIT_OR8(r4)
stw r5, INIT_BR8(r4)
stw r5, INIT_OR10(r4)
stw r5, INIT_BR10(r4)
stw r5, INIT_OR11(r4)
stw r5, INIT_BR11(r4)
mtspr LR, r29
bclr 20, 0
FUNC_END(romChipSelectInit)
/******************************************************************************
*
* memcSdram60xBusInit - initialize 60x Bus SDRAM.(do SDRAM test here)
*
* TBD
*
* RETURNS: N/A.
*/
FUNC_BEGIN(memcSdram60xBusInit)
mfspr r29, LR
lis r5, 0x0000
ori r5, r5, 0x0000
/*---------------------------------------------------------
* Initialize 60x Bus SDRAM
*--------------------------------------------------------*/
li r6, 0x27
stb r6, INIT_PSRT(r4)
/* OP(bit2~4): 100, precharge bank. RFEN(bit1): 0, no refresh */
lis r6, HIADJ(0xAB4E24A6) /* 101, precharge all banks */
addi r6, r6, LO(0xAB4E24A6)
stw r6, INIT_PSDMR1(r4)
/* perform an access */
li r6, 0xFF
stb r6, INIT_MEM0(r5)
#if defined(INCLUDE_CS4_60X_SDRAM)
li r6, 0xFF
lis r5, 0x0400
stb r6, INIT_MEM0(r5)
#endif
/* OP: 001, CBR refresh. RFEN: 0, no refresh */
lis r6, HIADJ(0x8B4E24A6)
addi r6, r6, LO(0x8B4E24A6)
stw r6, INIT_PSDMR2(r4)
/* perform 8 accesses */
li r6, 0xFF
lis r5, 0x0
stb r6, INIT_MEM1(r5)
li r6, 0xFF
lis r5, 0x0
stb r6, INIT_MEM2(r5)
li r6, 0xFF
lis r5, 0x0
stb r6, INIT_MEM3(r5)
li r6, 0xFF
lis r5, 0x0
stb r6, INIT_MEM4(r5)
li r6, 0xFF
lis r5, 0x0
stb r6, INIT_MEM5(r5)
li r6, 0xFF
lis r5, 0x0
stb r6, INIT_MEM6(r5)
li r6, 0xFF
lis r5, 0x0
stb r6, INIT_MEM7(r5)
li r6, 0xFF
lis r5, 0x0
stb r6, INIT_MEM8(r5)
#if defined(INCLUDE_CS4_60X_SDRAM)
li r6, 0xFF
lis r5, 0x0400
stb r6, INIT_MEM1(r5)
li r6, 0xFF
lis r5, 0x0400
stb r6, INIT_MEM2(r5)
li r6, 0xFF
lis r5, 0x0400
stb r6, INIT_MEM3(r5)
li r6, 0xFF
lis r5, 0x0400
stb r6, INIT_MEM4(r5)
li r6, 0xFF
lis r5, 0x0400
stb r6, INIT_MEM5(r5)
li r6, 0xFF
lis r5, 0x0400
stb r6, INIT_MEM6(r5)
li r6, 0xFF
lis r5, 0x0400
stb r6, INIT_MEM7(r5)
li r6, 0xFF
lis r5, 0x0400
stb r6, INIT_MEM8(r5)
#endif
/* OP: 011, mode register write. RFEN: 0, no refresh */
lis r6, HIADJ(0x9B4E24A6)
addi r6, r6, LO(0x9B4E24A6)
stw r6, INIT_PSDMR3(r4)
/* perform an access */
li r6, 0xFF
lis r5, 0x0
stb r6, INIT_MEM9(r5)
#if defined(INCLUDE_CS4_60X_SDRAM)
li r6, 0xFF
lis r5, 0x0400
stb r6, INIT_MEM9(r5)
#endif
/* OP: 000, normal operation. RFEN: 1, refresh */
lis r6, HIADJ(0xC34E24A6)
addi r6, r6, LO(0xC34E24A6)
stw r6, INIT_PSDMR4(r4)
/* return */
mtspr LR, r29
bclr 20, 0
FUNC_END(memcSdram60xBusInit)
/******************************************************************************
*
* memcSdramLocalBusInit - initialize Local Bus SDRAM.(do SDRAM test here)
*
* TBD
*
* RETURNS: N/A.
*/
FUNC_BEGIN(memcSdramLocalBusInit)
mfspr r29, LR
#if defined(INCLUDE_LOCAL_BUS_SDRAM)
lis r5, 0x0200
ori r5, r5, 0x0000
/*---------------------------------------------------------
* Initialize Local Bus SDRAM
*--------------------------------------------------------*/
li r6, 0x27
stb r6, INIT_LSRT(r4)
/* OP(bit2~4): 101, precharge all banks. RFEN(bit1): 0, no refresh */
lis r6, HIADJ(0x296A2256) /* 100, precharge bank*/
addi r6, r6, LO(0x296A2256)
stw r6, INIT_LSDMR1(r4)
/* perform an access */
li r6, 0xFF
lis r5, 0x2000
stb r6, INIT_MEM0(r5)
/* OP: 001, CBR refresh. RFEN: 0, no refresh */
lis r6, HIADJ(0x096A2256)
addi r6, r6, LO(0x096A2256)
stw r6, INIT_LSDMR2(r4)
/* perform 8 accesses */
li r6, 0xFF
lis r5, 0x2000
stb r6, INIT_MEM1(r5)
li r6, 0xFF
lis r5, 0x2000
stb r6, INIT_MEM2(r5)
li r6, 0xFF
lis r5, 0x2000
stb r6, INIT_MEM3(r5)
li r6, 0xFF
lis r5, 0x2000
stb r6, INIT_MEM4(r5)
li r6, 0xFF
lis r5, 0x2000
stb r6, INIT_MEM5(r5)
li r6, 0xFF
lis r5, 0x2000
stb r6, INIT_MEM6(r5)
li r6, 0xFF
lis r5, 0x2000
stb r6, INIT_MEM7(r5)
li r6, 0xFF
lis r5, 0x2000
stb r6, INIT_MEM8(r5)
/* OP: 011, mode register write. RFEN: 0, no refresh */
lis r6, HIADJ(0x196A2256)
addi r6, r6,LO(0x196A2256)
stw r6, INIT_LSDMR3(r4)
/* perform an access */
li r6, 0xFF
lis r5, 0x2000
stb r6, INIT_MEM9(r5)
/* OP: 000, normal operation. RFEN: 1, refresh */
lis r6, HIADJ(0x416A2256)
addi r6, r6, LO(0x416A2256)
stw r6, INIT_LSDMR4(r4)
#endif /* INCLUDE_LOCAL_BUS_SDRAM */
/* return */
mtspr LR, r29
bclr 20, 0
FUNC_END(memcSdramLocalBusInit)
/******************************************************************************
*
* romCacheInit - turn on instruction cache for faster FLASH ROM boots
*
*
*/
FUNC_BEGIN(romCacheInit)
mfspr r5, HID0
ori r5, r5, _PPC_HID0_ICE /* 0x00008000 */
isync
/*
* The setting of the instruction cache enable (ICE) bit must be
* preceded by an isync instruction to prevent the cache from being
* enabled or disabled while an instruction access is in progress.
*/
mtspr HID0, r5
sync
isync
bclr 20, 0
FUNC_END(romCacheInit)
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