sysalib.s

au1500开发的应用程序

/* sysALib.s - V100R001SCB system-dependent assembly routines */
	
/* Copyright 2002-2005 Founder Communications, Inc. */	
        .data
	.globl	copyright_wind_river
	.long	copyright_wind_river

/*
modification history
--------------------
01a,20jan05,fhchen  adapted from wrSbc8260Atm/sysAlib.s (ver 01c).
*/

/*
DESCRIPTION

This module contains system-dependent routines written in assembly
language.

This module must be the first specified in the ld command used to
build the system. The sysInit() routine is the system start-up code in
RAM.

Memory initialization is not performed in sysInit(), sysInit supporse
that bootloader has done this.
	
*/

#define _ASMLANGUAGE
		    
/* includes */
#include "vxWorks.h"
#include "sysLib.h"
#include "config.h"
#include "regs.h"	
#include "asm.h"
#include "drv/timer/m8260Clock.h"
	
	/* globals */

	FUNC_EXPORT(_sysInit)	/* start of system code */
        FUNC_EXPORT(sysPCGet)   /* get the value of the PC register */

	/* externals */

	FUNC_IMPORT(usrInit)

	_WRS_TEXT_SEG_START

/***************************************************************************
*
* sysInit - start after bootloaded
*
* This is the system start-up entry point for VxWorks in RAM, the
* first code executed after booting.  It disables interrupts, sets up
* the stack, and jumps to the C routine usrInit() in usrConfig.c.
*
* The initial stack is set to grow down from the address of sysInit().  This
* stack is used only by usrInit() and is never used again.  Memory for the
* stack must be accounted for when determining the system load address.
*
* SYNOPSIS
* \ss
* sysInit
*     (
*     void     /@ THIS IS NOT A CALLABLE ROUTINE @/
*     )
* \se
*
* NOTE: This routine should not be called by the user.
*
* RETURNS: N/A
*/

FUNC_BEGIN(_sysInit)

        /* disable external interrupts (by zeroing out msr) */
	xor	r5, r5, r5
	isync  
	mtmsr	r5
	isync  

        /*
	 * invalidate and disable data and instruction caches
	 *  ICE(bit16), DCE(bit17), ICFI(bit20), DCFI(bit21)
	 */
	mfspr	r6, HID0
	ori	r5, r5, (_PPC_HID0_ICE | _PPC_HID0_DCE)
	andc	r6, r6, r5	/* clear cache enable bits in r6 */
	mr	r5, r6
	ori     r5, r5, (_PPC_HID0_ICE | _PPC_HID0_DCE | _PPC_HID0_ICFI | _PPC_HID0_DCFI)
	sync
	mtspr	HID0, r5	/* invalidate both caches with 2 stores */
	isync
	mtspr	HID0, r6	/* leaving them both disabled */
	isync
	
	/* clear MMU  */
	mtspr   SPRG0, r3
	mtspr   SPRG1, r4
	bl	sysClearBATs
	bl	sysInvalidateTLBs
	bl	sysClearSegs
	mfspr   r3, SPRG0
	mfspr   r4, SPRG1

        /* Zero-out registers: r0 & SPRGs */
        xor     r0, r0, r0
	mtspr	SPRG0, r0
	mtspr	SPRG1, r0
	mtspr	SPRG2, r0
	mtspr	SPRG3, r0

	/* Turn on FP (temporarily) */
        ori	r3, r0, _PPC_MSR_FP
        mtmsr   r3
        sync

        /* Init the floating point control/status register */
        mtfsfi  7, 0x0
        mtfsfi  6, 0x0
        mtfsfi  5, 0x0
        mtfsfi  4, 0x0
        mtfsfi  3, 0x0
        mtfsfi  2, 0x0
        mtfsfi  1, 0x0
        mtfsfi  0, 0x0
        isync

        /* Initialize the floating point data registers to a known state */

        bl      initFPRs
       .long   0x3f800000      /* 1.0 ?? */
initFPRs:
        mflr    r3
        lfs     f0, 0(r3)
        lfs     f1, 0(r3)
        lfs     f2, 0(r3)
        lfs     f3, 0(r3)
        lfs     f4, 0(r3)
        lfs     f5, 0(r3)
        lfs     f6, 0(r3)
        lfs     f7, 0(r3)
        lfs     f8, 0(r3)
        lfs     f9, 0(r3)
        lfs     f10,0(r3)
        lfs     f11,0(r3)
        lfs     f12,0(r3)
        lfs     f13,0(r3)
        lfs     f14,0(r3)
        lfs     f15,0(r3)
        lfs     f16,0(r3)
        lfs     f17,0(r3)
        lfs     f18,0(r3)
        lfs     f19,0(r3)
        lfs     f20,0(r3)
        lfs     f21,0(r3)
        lfs     f22,0(r3)
        lfs     f23,0(r3)
        lfs     f24,0(r3)
        lfs     f25,0(r3)
        lfs     f26,0(r3)
        lfs     f27,0(r3)
        lfs     f28,0(r3)
        lfs     f29,0(r3)
        lfs     f30,0(r3)
        lfs     f31,0(r3)
        sync

	/*
	 * MSR: clear DCE,ICE,EE,DR,IR,ME -- set FP,RI
	 * Do not enable Machine Check until the vectors are set up.
	 */
	ori	r4, r0, (_PPC_MSR_FP | _PPC_MSR_RI)
	mtmsr   r4
	sync 

        /* fake a Decrementer Exception Handler (i.e. rfi @ 0x900) */
	lis 	r3, HI(0x4C000064)
	ori	r3, r3, LO(0x4C000064) /* load rfi (0x4c000064) to */
	stw 	r3, 0x900(r0)	     /* store rfi at 0x00000900  */

        /* Get internal memory map address */
	lis	r4, HIADJ(INTERNAL_MEM_MAP_ADDR+0x10000)
	addi	r4, r4, LO(INTERNAL_MEM_MAP_ADDR+0x10000)
	sync

        /* Set SCCR */
        lis	r5, HIADJ(M8260_SCCR_DFBRG_4)  /* divide by 4 */
	addi	r5, r5, LO(M8260_SCCR_DFBRG_4) /* divide by 4 */
	stw	r5, INIT_SCCR(r4)

	/* initialize the stack pointer */
	lis	sp, HI(RAM_LOW_ADRS)	/* NOTE:  sp = r1 */
	ori	sp, sp, LO(RAM_LOW_ADRS)
	addi	sp, sp, -FRAMEBASESZ	/* get frame stack */

	li	r3, BOOT_WARM_AUTOBOOT
	isync
	b	usrInit		/* never returns - starts up kernel */
                                /* (jumps to usrConfig.c )          */
FUNC_END(_sysInit)

/******************************************************************************
*
* sysPCGet - Get the value of the PC (Program Counter)
*
* This routine returns the value of the PC.
*
* SYNOPSIS
* \ss
* UINT32 sysPCGet
*     (
*     void
*     )
* \se
*
* RETURNS: the Program Counter Register (PC) value.
*/

FUNC_BEGIN(sysPCGet)
        mflr	r4		/* Save LR value */
        bl      Next		/* Set PC */
Next:
        mflr    r3		/* Get PC */
	mtlr    r4		/* Restor LR value */
	blr
FUNC_END(sysPCGet)

/***************************************************************************
*
* sysClearBATs - clear all the BAT's register
*
* This routine will zero the BAT's register.
*
* SYNOPSIS
* \ss
* void sysClearBATs
*     (
*     void
*     )
* \se
*
* SEE ALSO: sysInvalidateTLBs()
*
* RETURNS: N/A
*/

FUNC_BEGIN(sysClearBATs)

        /* zero out the BAT registers */
	xor	r3, r3, r3
	isync
	     
	mtspr	IBAT0U, r3	/* clear all upper BATS first */
	mtspr	IBAT1U, r3
	mtspr	IBAT2U, r3
	mtspr	IBAT3U, r3
	mtspr	DBAT0U, r3
	mtspr	DBAT1U, r3
	mtspr	DBAT2U, r3
	mtspr	DBAT3U, r3
		        
	mtspr	IBAT0L, r3	/* then clear lower BATS */
	mtspr	IBAT1L, r3
	mtspr	IBAT2L, r3
	mtspr	IBAT3L, r3
	mtspr	DBAT0L, r3
	mtspr	DBAT1L, r3
	mtspr	DBAT2L, r3
	mtspr	DBAT3L, r3
	isync
	
	blr
FUNC_END(sysClearBATs)

/***************************************************************************
*
* sysClearSegs - clearing all the SEG's register.
*
* This routine will zero the SEG's register.
*
* SYNOPSIS
* \ss
* void sysClearSegs
*     (
*     void
*     )
* \se
*
* RETURNS: N/A
*/

FUNC_BEGIN(sysClearSegs)

	/* Init the Segment registers */
	xor	r3, r3, r3
        isync
	     
        mtsr    0, r3
        mtsr    1, r3
        mtsr    2, r3
        mtsr    3, r3
        mtsr    4, r3
        mtsr    5, r3
        mtsr    6, r3
        mtsr    7, r3
        mtsr    8, r3
        mtsr    9, r3
        mtsr    10,r3
        mtsr    11,r3
        mtsr    12,r3
        mtsr    13,r3
        mtsr    14,r3
        mtsr    15,r3
        isync
	
	blr
FUNC_END(sysClearSegs)

/***************************************************************************
*
* sysInvalidateTLBs - invalidate all the BAT's register
*
* This routine will invalidate the BAT's register.
*
* SYNOPSIS
* \ss
* void sysInvalidateTLBs
*     (
*     void
*     )
* \se
*
* SEE ALSO: sysClearBATs()
*
* RETURNS: N/A
*/

FUNC_BEGIN(sysInvalidateTLBs)
	isync
	/* invalidate entries within both TLBs */
	li	r3, 128		/* 128 ? */
	mtctr	r3		/* CTR = 32  */
	xor	r3, r3, r3	/* r3 = 0    */
	isync			/* context sync req'd before tlbie */
								     
tlbloop:
	tlbie	r3
	sync			/* sync instr req'd after tlbie      */
	addi	r3, r3, 0x1000	/* increment bits 15-19. 0x1000 ? */
	bdnz	tlbloop		/* decrement CTR, branch if CTR != 0 */
	isync
	blr
FUNC_END(sysInvalidateTLBs)

#ifdef INCLUDE_CACHE_SUPPORT
#include "sysCacheLockALib.s"
#endif /* INCLUDE_CACHE_SUPPORT */