regau1500.def

au1500开发的应用程序

; Register definition file for Au1500
;
; Copyright 2002-2004 Founder Communications,Inc.
;
;modification history
;--------------------
; 01a,7apr05,fhchen  created from regau1k.def
;
;
;DESCRIPTION
;-----------
; Every entry consist of four fields.
;  name: user defined name of the register
;  type: the type of the register
; 	 GPR	general purpose register
;	 CP0	CP0 register
;	 MM	memory mapped register
;	 DMMx	direct memory mapped register with offset, x = 1..4
;		the base is defined in the configuration file, e.g. DMM1 0xB4000000
;        IMMx   indirect memory mapped register
;  addr: the number, adddress or offset of the register
;  size: the size of the register (8,16 or 32)
;
;REFERENCE
;---------
;1.Au1500 Processor Data Book(30361B), June 2003
; 
;name		type	addr		size
;-------------------------------------------
;
;
; CP0 Registers, Table 7 of Ref[1]
;
index   	CP0     0
random  	CP0     1
elo0    	CP0     2
elo1    	CP0     3
context 	CP0     4
pmask   	CP0     5
wired   	CP0     6
bad     	CP0     8
count   	CP0     9
ehi     	CP0     10
compare 	CP0     11
status  	CP0     12
cause   	CP0     13
epc     	CP0     14
prid    	CP0     15
config  	CP0     0x010
config1  	CP0     0x110
lladdr  	CP0     17
watchlo 	CP0     0x012
iwatchlo 	CP0     0x112
watchhi 	CP0     0x013
iwatchhi 	CP0     0x113
;reserved        CP0     20
;reserved        CP0     21
scratch 	CP0     22
debug   	CP0     23
depc    	CP0     24
perfcnt 	CP0     0x019
perfctrl 	CP0     0x119
;reserved        CP0     26
;reserved        CP0     27
dtag    	CP0     0x01c
ddata   	CP0     0x11c
itag    	CP0     0x01d
idata   	CP0     0x11d
eepc    	CP0     30
desave  	CP0     31
;
;
; Memory Controller Registers, Table 9 & Table 11
;
sdmode0 	DMM1    0x0000
sdmode1 	DMM1    0x0004
sdmode2 	DMM1    0x0008
sdaddr0 	DMM1    0x000c
sdaddr1 	DMM1    0x0010
sdaddr2 	DMM1    0x0014
sdrefcfg	DMM1    0x0018
sdprecmd	DMM1    0x001c
sdautoref       DMM1    0x0020
sdwrmd0 	DMM1    0x0024
sdwrmd1 	DMM1    0x0028
sdwrmd2 	DMM1    0x002c
sdsleep 	DMM1    0x0030
sdsmcke 	DMM1    0x0034
;
stcfg0  	DMM1    0x1000
sttime0 	DMM1    0x1004
staddr0 	DMM1    0x1008
stcfg1  	DMM1    0x1010
sttime1 	DMM1    0x1014
staddr1 	DMM1    0x1018
stcfg2  	DMM1    0x1020
sttime2 	DMM1    0x1024
staddr2 	DMM1    0x1028
stcfg3  	DMM1    0x1030
sttime3 	DMM1    0x1034
staddr3 	DMM1    0x1038
;
; DMA Controller Registers, Table 26 & Table 27
;
dma0_moderead   DMM1    0x2000
dma0_modeset    DMM1    0x2000
dma0_modeclr    DMM1    0x2004
dma0_peraddr    DMM1    0x2008
dma0_buf0addr   DMM1    0x200c
dma0_buf0size   DMM1    0x2010
dma0_buf1addr   DMM1    0x2014
dma0_buf1size   DMM1    0x2018
;
dma1_moderead   DMM1    0x2100
dma1_modeset    DMM1    0x2100
dma1_modeclr    DMM1    0x2104
dma1_peraddr    DMM1    0x2108
dma1_buf0addr   DMM1    0x210c
dma1_buf0size   DMM1    0x2110
dma1_buf1addr   DMM1    0x2114
dma1_buf1size   DMM1    0x2118
;
dma2_moderead   DMM1    0x2200
dma2_modeset    DMM1    0x2200
dma2_modeclr    DMM1    0x2204
dma2_peraddr    DMM1    0x2208
dma2_buf0addr   DMM1    0x220c
dma2_buf0size   DMM1    0x2210
dma2_buf1addr   DMM1    0x2214
dma2_buf1size   DMM1    0x2218
;
dma3_moderead   DMM1    0x2300
dma3_modeset    DMM1    0x2300
dma3_modeclr    DMM1    0x2304
dma3_peraddr    DMM1    0x2308
dma3_buf0addr   DMM1    0x230c
dma3_buf0size   DMM1    0x2310
dma3_buf1addr   DMM1    0x2314
dma3_buf1size   DMM1    0x2318
;
dma4_moderead   DMM1    0x2400
dma4_modeset    DMM1    0x2400
dma4_modeclr    DMM1    0x2404
dma4_peraddr    DMM1    0x2408
dma4_buf0addr   DMM1    0x240c
dma4_buf0size   DMM1    0x2410
dma4_buf1addr   DMM1    0x2414
dma4_buf1size   DMM1    0x2418
;
dma5_moderead   DMM1    0x2500
dma5_modeset    DMM1    0x2500
dma5_modeclr    DMM1    0x2504
dma5_peraddr    DMM1    0x2508
dma5_buf0addr   DMM1    0x250c
dma5_buf0size   DMM1    0x2510
dma5_buf1addr   DMM1    0x2514
dma5_buf1size   DMM1    0x2518
;
dma6_moderead   DMM1    0x2600
dma6_modeset    DMM1    0x2600
dma6_modeclr    DMM1    0x2604
dma6_peraddr    DMM1    0x2608
dma6_buf0addr   DMM1    0x260c
dma6_buf0size   DMM1    0x2610
dma6_buf1addr   DMM1    0x2614
dma6_buf1size   DMM1    0x2618
;
dma7_moderead   DMM1    0x2700
dma7_modeset    DMM1    0x2700
dma7_modeclr    DMM1    0x2704
dma7_peraddr    DMM1    0x2708
dma7_buf0addr   DMM1    0x270c
dma7_buf0size   DMM1    0x2710
dma7_buf1addr   DMM1    0x2714
dma7_buf1size   DMM1    0x2718
;
; Interrupt Controller Registers, Table 32
;
ic0_cfg0rd      DMM2    0x0040
ic0_cfg0set     DMM2    0x0040
ic0_cfg0clr     DMM2    0x0044
ic0_cfg1rd      DMM2    0x0048
ic0_cfg1set     DMM2    0x0048
ic0_cfg1clr     DMM2    0x004c
ic0_cfg2rd      DMM2    0x0050
ic0_cfg2set     DMM2    0x0050
ic0_cfg2clr     DMM2    0x0054
ic0_req0int     DMM2    0x0054
ic0_srcrd       DMM2    0x0058
ic0_srcset      DMM2    0x0058
ic0_srcclr      DMM2    0x005c
ic0_req1int     DMM2    0x005c
ic0_assignrd    DMM2    0x0060
ic0_assignset   DMM2    0x0060
ic0_assignclr   DMM2    0x0064
ic0_wakerd      DMM2    0x0068
ic0_wakeset     DMM2    0x0068
ic0_wakeclr     DMM2    0x006c
ic0_maskrd      DMM2    0x0070
ic0_maskset     DMM2    0x0070
ic0_maskclr     DMM2    0x0074
ic0_risingrd    DMM2    0x0078
ic0_risingclr   DMM2    0x0078
ic0_fallingrd   DMM2    0x007c
ic0_fallingclr  DMM2    0x007c
ic0_testbit     DMM2    0x0080
;
ic1_cfg0rd      DMM3    0x0040
ic1_cfg0set     DMM3    0x0040
ic1_cfg0clr     DMM3    0x0044
ic1_cfg1rd      DMM3    0x0048
ic1_cfg1set     DMM3    0x0048
ic1_cfg1clr     DMM3    0x004c
ic1_cfg2rd      DMM3    0x0050
ic1_cfg2set     DMM3    0x0050
ic1_cfg2clr     DMM3    0x0054
ic1_req0int     DMM3    0x0054
ic1_srcrd       DMM3    0x0058
ic1_srcset      DMM3    0x0058
ic1_srcclr      DMM3    0x005c
ic1_req1int     DMM3    0x005c
ic1_assignrd    DMM3    0x0060
ic1_assignset   DMM3    0x0060
ic1_assignclr   DMM3    0x0064
ic1_wakerd      DMM3    0x0068
ic1_wakeset     DMM3    0x0068
ic1_wakeclr     DMM3    0x006c
ic1_maskrd      DMM3    0x0070
ic1_maskset     DMM3    0x0070
ic1_maskclr     DMM3    0x0074
ic1_risingrd    DMM3    0x0078
ic1_risingclr   DMM3    0x0078
ic1_fallingrd   DMM3    0x007c
ic1_fallingclr  DMM3    0x007c
ic1_testbit     DMM3    0x0080
;
; System Control Registers, Table 58/60/61/63
;
sys_freqctrl0   MM      0xb1900020
sys_freqctrl1   MM      0xb1900024
sys_clksrc      MM      0xb1900028
sys_cpupll      MM      0xb1900060
sys_auxpll      MM      0xb1900064
;
sys_toytrim     MM      0xb1900000
sys_toywrite    MM      0xb1900004
sys_toymatch0   MM      0xb1900008
sys_toymatch1   MM      0xb190000c
sys_toymatch2   MM      0xb1900010
sys_cntrctrl    MM      0xb1900014
sys_toyread     MM      0xb1900040
;
sys_rtctrim     MM      0xb1900044
sys_rtcwrite    MM      0xb1900048
sys_rtcmatch0   MM      0xb190004c
sys_rtcmatch1   MM      0xb1900050
sys_rtcmatch2   MM      0xb1900054
sys_rtcread     MM      0xb1900058
;
sys_pinfunc     MM      0xb190002c
;
sys_trioutrd    MM      0xb1900100
sys_trioutclr   MM      0xb1900100
sys_outputrd    MM      0xb1900108
sys_outputset   MM      0xb1900108
sys_outputclr   MM      0xb190010c
sys_pinstaterd  MM      0xb1900110
sys_pininputen  MM      0xb1900110
;
sys_scratch0    MM      0xb1900018
sys_scratch1    MM      0xb190001c
sys_wakemsk     MM      0xb1900034
sys_endian      MM      0xb1900038
sys_powerctrl   MM      0xb190003c
sys_wakesrc     MM      0xb190005c
sys_slppwr      MM      0xb1900078
sys_sleep       MM      0xb190007c
; 
; UART registers, table 51/52
;
uart0_rxdata    MM      0xb1100000
uart0_txdata    MM	0xb1100004
uart0_inten	MM	0xb1100008
uart0_intcause  MM	0xb110000c
uart0_fifoctrl	MM	0xb1100010
uart0_linectrl	MM	0xb1100014
uart0_linestat	MM	0xb110001c
uart0_clkdiv	MM	0xb1100028
uart0_enable    MM      0xb1100100  
uart3_rxdata    MM      0xb1400000
uart3_txdata    MM	0xb1400004
uart3_inten	MM	0xb1400008
uart3_intcause  MM	0xb140000c
uart3_fifoctrl	MM	0xb1400010
uart3_linectrl	MM	0xb1400014
uart3_mdmctrl	MM	0xb1400018
uart3_linestat	MM	0xb140001c
uart3_mdmstat	MM	0xb1400020
uart3_autoflow	MM	0xb1400024
uart3_clkdiv	MM	0xb1400028
uart3_enable    MM      0xb1400100
; 
; MAC registers, table 44/45/
;
mac0_control    MM      0xb1500000
mac0_addrhigh   MM      0xb1500004
mac0_addrlow    MM      0xb1500008
mac0_hashhigh   MM      0xb150000c
mac0_hashlow    MM      0xb1500010
mac0_miictrl    MM      0xb1500014
mac0_miidata    MM      0xb1500018
mac0_miiflow    MM      0xb150001c
mac0_vlan1      MM      0xb1500020
mac0_vlan2      MM      0xb1500024
mac0_en         MM      0xb1520000
mac3_control    MM      0xb1510000
mac3_addrhigh   MM      0xb1510004
mac3_addrlow    MM      0xb1510008
mac3_hashhigh   MM      0xb151000c
mac3_hashlow    MM      0xb1510010
mac3_miictrl    MM      0xb1510014
mac3_miidata    MM      0xb1510018
mac3_miiflow    MM      0xb151001c
mac3_vlan1      MM      0xb1510020
mac3_vlan2      MM      0xb1510024
mac3_en         MM      0xb1520004