v100r001cpe-bdi2000.cfg

au1500开发的应用程序

; bdiGDB configuration file for V100R001 CPE board (AU1500)
; 
; Copyright 2002-2005 Founder Communications,Inc.
;
;modification history
;--------------------
; 01a,12apr05,fhchen  written 
;
;
;DESCRIPTION
;-----------
; V100R001 CPE board support three flash scheme via jumper:
; - RCS0 connected to AM29LV040(2 piece, each is 8 bit wide), RCS3 not connected
; - RCS0 connected to Intel 28F128J3(1 piece, 16 bit wide), RCS3 not connected
; - RCS0 connected to AM29LV040, and RCS3 connected to 28F128J3
; 
; This configuration file default to the third scheme. If use the first scheme,
; change the [INIT] and [FLASH] section accordingly.

[INIT]
WCP0    12          0x00000000  ; status[IE], disable interrupts
;
; Setup CPU PLL to 396 MHz, 396/12 = 0x21
WM32    0xB1900060  0x00000021  ; CPU_PLL Configuration
DELAY   100                     ; should wait for 20us, we wait for 100ms
;
; Setup Endianess
WM32    0xB1900038  0x00000001  ; Set to Little Endian
WCP0    16          0x00000003  ; config0[K0], KSEG0 cacheable
; 
; Setup Static Bus Controller, 
; endian(bit9): 0 - little, 1- big
; width(bit6): 0 - 32bit, 1 - 16bit
WM32    0xB4001000  0x00000043  ; RCS0 AM29LV040 Configuration
WM32	 0xB4001004 0x22080B20	; RCS0 Timing,0x7F0FFFFF
WM32    0xB4001008  0x11FC3FFC  ; RCS0 Address
;WM32    0xB4001000  0x00000043  ; RCS0 28F128J3 Configuration
;WM32	0xB4001004  0x22080B20	; RCS0 Timing, 0x7F0FFFFF worst case
;WM32    0xB4001008  0x11F03FC0  ; RCS0 Address
;WM32    0xB4001010  0x00000000  ; RCS1 Configuration
;WM32    0xB4001014  0x22080A20  ; RCS1 Timing
WM32    0xB4001010  0x00000100  ; RCS1 Configuration, system bus/4
WM32    0xB4001014  0x7F0FFFFF  ; RCS1 Timing, 0x7F0FFFFF worst case
WM32    0xB4001018  0x10303FFF  ; RCS1 Address
WM32    0xB4001020  0x00000040  ; RCS2 Configuration
WM32    0xB4001024  0x22080A20	; RCS2 Timing
WM32    0xB4001028  0x11D03FFF  ; RCS2 Address
WM32    0xB4001030  0x00000043  ; RCS3 28F128J3 Configuration
WM32    0xB4001034  0x22080B20  ; RCS3 Timing
WM32    0xB4001038  0x11E03FC0  ; RCS3 Address
;
; Setup SDRAM Controller
WM32    0xB4000000  0x005522A9  ; CS0 mode configuration, CAS latency is 2
                                ; if choose 3, change to 0x005522AA.
WM32    0xB4000004  0x00000000  ; CS1 mode configuration
WM32    0xB4000008  0x00000000  ; CS2 mode configuration
WM32    0xB400000C  0x001003F8  ; CS0 address, 32MB at 0x00000000
WM32    0xB4000010  0x00000000  ; CS1 address,
WM32    0xB4000014  0x00000000  ; CS2 address,
WM32    0xB4000018  0x7400186A  ; Program refresh (disabled)
WM32    0xB400001C  0x00000000  ; Precharge all banks
WM32    0xB4000020  0x00000000  ; Issue two auto refreshes
WM32    0xB4000020  0x00000000  ; Issue two auto refreshes
WM32    0xB4000018  0x66000C24  ; Program refresh again (enabled)
WM32    0xB4000024  0x00000023  ; CS0 set mode, CAS latency is 2
                                ; if choose 3, change to 0x00000033
WM32    0xB4000028  0x00000000  ; CS1 set mode
WM32    0xB400002C  0x00000000  ; CS2 set mode

[TARGET]
JTAGCLOCK   1                  ; use 8MHz JTAG clock, 0 - 16MHz, 3 - 4.1MHz
CPUTYPE     AU1000
ENDIAN      LITTLE             ; LITTLE or BIG endian
BDIMODE     AGENT              ; AGENT | LOADONLY
RESET       HARD               ; NONE | JTAG | HARD
;STARTUP     RUN              ; RESET | STOP | RUN
STARTUP     RESET              ; RESET | STOP | RUN
;STARTUP     STOP 8000              ; RESET | STOP | RUN
;WAKEUP      1000               ;
;BREAKMODE   HARD                ; SOFT | HARD, HARD uses hardware breakpoints
BREAKMODE   SOFT               ; SOFT | HARD, HARD uses hardware breakpoints
;STEPMODE    HWBP                ; JTAG | HWBP | SWBP
STEPMODE    JTAG                ; JTAG | HWBP | SWBP
VECTOR      CATCH              ; catch unhandled exceptions
WORKSPACE   0xA1FF0000         ; workspace in target RAM for fast download, 
                               ; at least 64B
REGLIST     STD CP0            ; standard and cp0 registers all sent to GDB
;SIO        7 9600              ; enable serial I/O routing, TCP port 7, 9600 baud

[HOST]
IP          192.168.80.126
FILE        D:\project\V100R001\CPE\debug\vxWorks
                               ; for 'load' command
FORMAT      ELF                ; SREC, BIN, AOUT, ELF or ROM
LOAD        MANUAL             ; load code MANUAL or AUTO after reset
DEBUGPORT   2001
PROMPT	    V100R001CPE> 
DUMP	    D:\project\V100R001\CPE\debug\memdump
TELNET      ECHO               ; ECHO | NOECHO

[FLASH]
CHIPTYPE    AM29F              ; AM29LV040
CHIPSIZE    0x00080000         ; 512KB, one pieces
BUSWIDTH    16                 ; 8bit*2
;CHIPTYPE    STRATAX16          ; 28F128J3
;CHIPSIZE    0x01000000         ; 16MB
;BUSWIDTH    16                 ; 16bit wide
FORMAT      BIN                ; SREC, BIN, AOUT or ELF
FILE        D:\project\V100R001\CPE\debug\bootrom.bin
                               ; for 'prog' command
WORKSPACE   0xA1FC0000         ; workspace in target RAM for fast programming algorithm, 
                               ; at least 4KB.

; erase 1MB for bootrom, 'erase' command use this. 
; apply to RCS0 (AM29LV040*2 or 28F128J3)

ERASE       0xBFC00000         ; erase sector 0
ERASE       0xBFC20000         ; erase sector 1, 128KB per block
ERASE       0xBFC40000
ERASE       0xBFC60000
ERASE       0xBFC80000
ERASE       0xBFCA0000
ERASE       0xBFCC0000
ERASE       0xBFCE0000
;ERASE      0xBFC00000  CHIP

; try erase 1MB of RCS3 (28F128J3)

;ERASE       0xBE000000         ; erase sector 0
;ERASE       0xBE020000         ; erase sector 1, 128KB per block
;ERASE       0xBE040000
;ERASE       0xBE060000
;ERASE       0xBE080000
;ERASE       0xBE0A0000
;ERASE       0xBE0C0000
;ERASE       0xBE0E0000
;ERASE      0xBE000000  CHIP

[REGS]
DMM1        0xB4000000         ; memory controller block base address
DMM2        0xB0400000         ; interrupt controller 0 base address
DMM3        0xB1800000         ; interrupt controller 1 base address
FILE        regau1500.def      ; register file