v100r001bts-bdi2000.cfg

au1500开发的应用程序

; bdiGDB configuration file for V100R001 CHB and SCB board (MPC8260)
; 
; Copyright 2002-2005 Founder Communications,Inc.
;
;modification history
;--------------------
; 01a,26may05,fhchen  written from est8260.cfg and vads8260.cfg 
;
;
;DESCRIPTION
;-----------
; This file only initialize one SDRAM region, namely those 64MB on CS3,
; CS4(64MB on 60x bus) and CS5(32MB on local bus) not initialized.


[INIT]
;
; Init core reigister
;
WREG    MSR             0x00000000      ; clear MSR
WM32    0x0F0101A8      0x0F000000      ; IMMR : internal space @ 0x0F000000
WM32    0x0F010004      0xFFFFFFC3      ; SYPCR: bit29, disable watchdog
WM32    0x0F010C80      0x00000001      ; SCCR : normal operations, DFBRG = 1
;WM32    0x0F010024      0x70000000      ; BCR  : 
;WM32    0x0F010024      0x004C0000      ; BCR  : 
;
; Init memory controller
;
; - init all on board flash
;
WM32    0x0F010104      0xFFF00C56      ; OR0: 5 clock cycles wait states
WM32    0x0F010100      0xFFF00801      ; BR0: AM29LV040B, 8bit, 512KB from 0xFFF00000
WM32    0x0F01010C      0xFF000C56      ; OR1:
WM32    0x0F010108      0x10001001      ; BR1: 28F128J3, 16bit, 16MB from 0x10000000
WM32    0x0F010114      0xFFF00C56      ; OR2:
WM32    0x0F010110      0x11001001      ; BR2: 28F128J3, 16bit, 16MB from 0x11000000 
;
; - init one 60x bus SDRAM
;
WM16    0x0F010184      0x1800          ; MPTPR: divide system clock by 25 to
                                        ; get timers input clock 
WM8     0x0F01019C      0x27            ; PSRT : divide MPTPR output by 40 to
                                        ; get 60x refresh timer period [!]
WM32    0x0F01011C      0xFC002CD0      ; OR3  : 4 banks, row start at A6, 
WM32    0x0F010118      0x00000041      ; BR3  : SDRAM, 64bit, 64MB from 0x00000000

WM32    0x0F010190      0x834E24A6
WM32    0x0F010190      0xAB4E24A6      ; PSDMR: precharge all bank, OP is 101
WM8     0x00000000      0xFF            ; Access SDRAM
WM32    0x0F010190      0x8B4E24A6      ; PSDMR: CBR refresh, OP is 001
WM8     0x00000000      0xFF            ; Access SDRAM
WM8     0x00000001      0xFF            ; Access SDRAM
WM8     0x00000002      0xFF            ; Access SDRAM
WM8     0x00000003      0xFF            ; Access SDRAM
WM8     0x00000004      0xFF            ; Access SDRAM
WM8     0x00000005      0xFF            ; Access SDRAM
WM8     0x00000006      0xFF            ; Access SDRAM
WM8     0x00000007      0xFF            ; Access SDRAM
WM32    0x0F010190      0x9B4E24A6      ; PSDMR: mode set, OP is 011
WM8     0x00000009      0xFF            ; Access SDRAM
WM32    0x0F010190      0xC34E24A6      ; PSDMR: enable refresh, normal operation, OP is 000
;
; - init one local bus SDRAM
;
WM8     0x0F0101A4      0x27            ; LSRT : divide MPTPR output by 40 to 
                                        ; get local bus refresh timer period
WM32    0x0F01012C      0xFE002CD0      ; OR5: 4 banks, row start at A6
WM32    0x0F010128      0x20001861      ; BR5: SDRAM, 32bit, 32MB from 0x20000000

WM32    0x0F010194      0x296A2256      ; LSDMR: precharge all bank, OP is 101
WM8     0x20000000      0xFF            ; Access SDRAM
WM32    0x0F010194      0x096A2256      ; LSDMR: CBR refresh, OP is 001
WM8     0x20000000      0xFF            ; Access SDRAM
WM8     0x20000001      0xFF            ; Access SDRAM
WM8     0x20000002      0xFF            ; Access SDRAM
WM8     0x20000003      0xFF            ; Access SDRAM
WM8     0x20000004      0xFF            ; Access SDRAM
WM8     0x20000005      0xFF            ; Access SDRAM
WM8     0x20000006      0xFF            ; Access SDRAM
WM8     0x20000007      0xFF            ; Access SDRAM
WM32    0x0F010194      0x196A2256      ; LSDMR: mode register write, OP is 011
WM8     0x20000009      0xFF            ; Access SDRAM
WM32    0x0F010194      0x416A2256      ; LSDMR: normal operation, OP is 000
;
; - init two DSP CS [only on CHB]
;
WM32    0x0F01013C      0xFFFF0C56      ; OR7:
WM32    0x0F010138      0x60001801      ; BR7: , 32bit,64KB from 0x60000000 
;WM32    0x0F010138      0x60001001      ; BR7: , 16bit,64KB from 0x60000000 
WM32    0x0F010144      0xFFFF0C56      ; OR8:
WM32    0x0F010140      0x70001801      ; BR8: , 32bit,64KB from 0x70000000 
;WM32    0x0F010140      0x70001001      ; BR8: , 16bit,64KB from 0x70000000 
;
; - [temp] try to init FPGA CS
;
;WM32    0x0F01014C      0xFFFF0C56      ; OR9:
;WM32    0x0F010148      0x40001000      ; BR9: xc3s1000, 16bit, 64KB from 0x40000000, disabled
;
;
[TARGET]
CPUTYPE     8260        ; the CPU type (603EV,750,8240,8260 etc)
JTAGCLOCK   0           ; use 16.6 MHz JTAG clock (1 - 8.3M, 2 - 5.5M, 3 - 4.1M)
BDIMODE     AGENT     	; the BDI working mode (LOADONLY | AGENT)
STARTUP     RESET       ; RESET | STOP | RUN
;;STARTUP     STOP
BOOTADDR    0xFFF00100  ; 0xFFF00100 | 0x00000100
WORKSPACE   0x03FC0000	; use reserved memory as workspace,should > 256B
BREAKMODE   SOFT      	; SOFT or HARD, HARD uses PPC hardware breakpoints,
                        ; only 1 hard breakpoints supported.
STEPMODE    TRACE       ; TRACE | HWBP                        
VECTOR      CATCH       ; catch unhandled exceptions
;DCACHE      FLUSH	; data cache flushing (FLUSH | NOFLUSH)
DCACHE      NOFLUSH	; data cache flushing (FLUSH | NOFLUSH)
POWERUP     5000        ; delay before trying JTAG communication in ms
;WAKEUP      1000
;PARITY      OFF
REGLIST     ALL         ; STD | FPR | SR | BAT | SPR | AUX | ALL
;
;
[HOST]
IP          192.168.81.10
FILE        D:\project\V100R001\CHB\debug\vxWorks
FORMAT      ELF         ; SREC, BIN, AOUT, ELF, IMAGE* or ROM
LOAD        MANUAL      ; load code MANUAL or AUTO after reset
DEBUGPORT   2001
PROMPT      V100R001BTS> 
DUMP        D:\project\V100R001\CHB\debug\memdump
TELNET      ECHO        ; ECHO | NOECHO
;
;
[FLASH]
CHIPTYPE    AM29F       ; AM29LV040B
CHIPSIZE    0x00080000  ; 512KB, one piece
BUSWIDTH    8           ; 8bit
FORMAT      BIN
FILE        D:\project\V100R001\CHB\debug\bootrom.bin
WORKSPACE   0x03FC0000  ; use reserved memory as workspace, should > 2KB
;
; AM29LV040B, eight sectors * 64KB/sector
ERASE       0xFFF00000  ; erase sector 0
ERASE       0xFFF10000  ; erase sector 1
ERASE       0xFFF20000  ; erase sector 2
ERASE       0xFFF30000  ; erase sector 3 
ERASE       0xFFF40000  ; erase sector 4
ERASE       0xFFF50000  ; erase sector 5
ERASE       0xFFF60000  ; erase sector 6
;ERASE       0xFFF70000  ; erase sector 7,!WARNING: this sector hold boot line!
;
;
[REGS]
DMM1        0x0F000000
FILE        reg8260.def