comm.h
来自「S3C24A0的完整BSP包,对开发此芯片的开发者很有用.」· C头文件 代码 · 共 432 行
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432 行
//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*
************************************************************************
*
* COMM.h
*
*
* (C) Copyright Samsung Electronics.
*
*
* (ep)
*
*************************************************************************
*/
#ifndef COMM_H
#define COMM_H
#define S24A0UART_FIFO_SIZE 64
#if 0
/*
* Size of the 16550 read and write FIFOs
*/
/*
* The programming interface to a UART (COM serial port)
* consists of eight consecutive registers.
* These are the port offsets from the UART's base I/O address.
*/
typedef enum comPortRegOffsets {
XFER_REG_OFFSET = 0,
INT_ENABLE_REG_OFFSET = 1,
INT_ID_AND_FIFO_CNTRL_REG_OFFSET = 2,
LINE_CONTROL_REG_OFFSET = 3,
MODEM_CONTROL_REG_OFFSET = 4,
LINE_STAT_REG_OFFSET = 5,
MODEM_STAT_REG_OFFSET = 6,
SCRATCH_REG_OFFSET = 7
} comPortRegOffset;
/*
* Bits in the UART Interrupt-Id register.
*/
#define INTID_INTERRUPT_NOT_PENDING (UCHAR)(1 << 0)
/*
* Values for bits 2-1 of Interrupt-Id register:
* 00 Modem Stat reg interrupt
* 01 Transmitter holding reg interrupt
* 10 Receive data ready interrupt
* 11 Receive line status interrupt
*
*/
#define INTID_INTIDMASK (UCHAR)(3 << 1)
#define INTID_MODEMSTAT_INT (UCHAR)(0 << 1)
#define INTID_XMITREG_INT (UCHAR)(1 << 1)
#define INTID_RCVDATAREADY_INT (UCHAR)(2 << 1)
#define INTID_RCVLINESTAT_INT (UCHAR)(3 << 1)
/*
* Bits in the UART line-status register.
*/
#define LINESTAT_DATAREADY (UCHAR)(1 << 0)
#define LINESTAT_OVERRUNERROR (UCHAR)(1 << 1)
#define LINESTAT_PARITYERROR (UCHAR)(1 << 2)
#define LINESTAT_FRAMINGERROR (UCHAR)(1 << 3)
#define LINESTAT_BREAK (UCHAR)(1 << 4)
#define LINESTAT_XMIT_HOLDING_REG_EMPTY (UCHAR)(1 << 5)
#define LINESTAT_XMIT_SHIFT_AND_HOLDING_REG_EMPTY (UCHAR)(1 << 6)
/*
* These are bits in the UART's interrupt-enable register (INT_ENABLE_REG_OFFSET).
*/
#define DATA_AVAIL_INT_ENABLE (1 << 0)
#define READY_FOR_XMIT_INT_ENABLE (1 << 1)
#define RCV_LINE_STAT_INT_ENABLE (1 << 2)
#define MODEM_STAT_INT_ENABLE (1 << 3)
#define RCV_MODE_INTS_ENABLE (DATA_AVAIL_INT_ENABLE)
#define XMIT_MODE_INTS_ENABLE (READY_FOR_XMIT_INT_ENABLE|DATA_AVAIL_INT_ENABLE)
#define ALL_INTS_ENABLE (RCV_MODE_INTS_ENABLE | XMIT_MODE_INTS_ENABLE)
#define ALL_INTS_DISABLE 0
/*
* These are fine-tuning parameters for the COM port ISR.
* Number of times we poll a COM port register waiting
* for a value which may/must appear.
*/
#endif
// following two cts values are read from modem control register.
#define COM24A0_MSR_CTS 0x1
#define COM24A0_MSR_DCTS 0x4
// following two cts values are read from modem GIO port.
#define COM24A0_MSR_DSR 0x2
#define COM24A0_MSR_DDSR 0x8
///////++ UART Line CONTROL REGISTER ++
// Line control register bitvalue mask
#define SER24A0_PARITY_MASK 0x38
#define SER24A0_STOPBIT_MASK 0x4
#define SER24A0_DATABIT_MASK 0x3
#define SER24A0_IRMODE_MASK 0x40
// Fifo Status TX
#define SER24A0_TXFIFOSTAT_MASK 0x3f00 // if s3c2410, 0xf0
//
#define SER24A0_TX_FIFOFULL 0x4000 // if s3c2410, 0x200
#define SER24A0_TX_FIFOCNT_MASK 0x3f00 // if s3c2410, 0xf0
#define SER24A0_TX_FIFOCNT_BIT_SHIFT 8 // if s3c2410, 4
#define SER24A0_TX_FIFO_DEPTH 64 // if s3c2410, 16
// Fifo Status RX
#define SER24A0_RXFIFOSTAT_MASK 0x3f
//
#define SER24A0_RX_FIFOFULL 0x40
#define SER24A0_RX_FIFOCNT_MASK 0x3f
#define SER24A0_RX_FIFOCNT_BIT_SHIFT 0
#define SER24A0_RX_FIFO_DEPTH 64 // if s3c2410, 16
// TBD : I'm not sure the following value..
#define SER24A0_INT_INVALID 0x5a5affff
// TBD : I'm not sure the value.
// UMCONn - UART Modem Control Register
//
// Modem control register
#define SER24A0_AFC (0x10)
#define SER24A0_RTS 0x1
// UCONn - UART Control Register
//
//Receive Mode
#define RX_MODE_MASK (0x3) // 0b11
#define RX_DISABLE (0x0) // 0b00
#define RX_INTPOLL (0x1) // 0b01
#define RX_DMA0 (0x2) // 0b10 For UART0 only
#define RX_DMA1 (0x3) // 0b11 For UART1 only
//Transmit Mode
#define TX_MODE_MASK (0x3 << 2)
#define TX_DISABLE (0x0 << 2)
#define TX_INTPOLL (0x1 << 2)
#define TX_DMA0 (0x2 << 2) // For UART0 Only
#define TX_DMA1 (0x3 << 2) // For UART1 Only
//Send Break Signal
#define BS_MASK (0x01 << 4)
#define BS_NORM (0x00 << 4)
#define BS_SEND (0x01 << 4)
//Loop-back Mode
#define LB_MASK (0x01 << 5)
#define LB_NORM (0x00 << 5)
#define LB_MODE (0x01 << 5)
//Rx Error Status Interrupt Enable
#define RX_EINT_MASK (0x01 << 6)
#define RX_EINTGEN_OFF (0x00 << 6)
#define RX_EINTGEN_ON (0x01 << 6)
//Rx Time Out Enable
#define RX_TIMEOUT_MASK (0x01 << 7)
#define RX_TIMEOUT_DIS (0x00 << 7)
#define RX_TIMEOUT_EN (0x01 << 7)
//Rx Interrupt Type
#define RX_INTTYPE_MASK (0x01 << 8)
#define RX_INTTYPE_PUSE (0x00 << 8)
#define RX_INTTYPE_LEVEL (0x01 << 8)
//Tx Interrupt Type
#define TX_INTTYPE_MASK (0x01 << 9)
#define TX_INTTYPE_PUSE (0x00 << 9)
#define TX_INTTYPE_LEVEL (0x01 << 9)
// Clock selection
#define CS_MASK (0x01 << 10)
#define CS_PCLK (0x00 << 10)
#define CS_UCLK (0x01 << 10)
// ULCONn : UART LINE CONTROL REGISTER BITS
#define ULCON_INFRARED_MODE (1<<6) //0x40
#define ULCON_NOPARITY_MODE (0<<3)
#define ULCON_ODD_PARITY (4<<3) //0x20
#define ULCON_EVEN_PARITY (5<<3) //0x28
#define ULCON_PARITY_ONE (6<<3) //0x30
#define ULCON_PARITY_ZERO (7<<3) //0x38
#define ULCON_ONE_STOP_BIT (0<<2)
#define ULCON_TWO_STOP_BIT (1<<2) //0x04
#define ULCON_5BIT_WORD_LEN (0<<0)
#define ULCON_6BIT_WORD_LEN (1<<0)
#define ULCON_7BIT_WORD_LEN (2<<0)
#define ULCON_8BIT_WORD_LEN (3<<0)
// UCONn : UART CONTROL REGISTER
#define UCON_CLK_SEL_PCLK (0<<10)
#define UCON_CLK_SEL_UCLK (1<<10)
#define UCON_TX_INT_PULSE (0<<9)
#define UCON_TX_INT_LEVEL (1<<9)
#define UCON_RX_INT_PULSE (0<<8)
#define UCON_RX_INT_LEVEL (1<<8)
#define UCON_RX_TIMEOUT_ENABLE (1<<7)
#define UCON_RX_TIMEOUT_DISABLE (0<<7)
#define UCON_RX_ERRSTAT_INT_ENABLE (1<<6)
#define UCON_RX_ERRSTAT_INT_DISABLE (0<<6)
#define UCON_LOOPBACK_MODE (1<<5)
#define UCON_NORMAL_MODE (0<<5)
#define UCON_SENDBREAK_SIGNAL (1<<4)
#define UCON_DONTSENDBREAK_SIGNAL (0<<4)
#define UCON_TX_MODE_DISABLE (0<<2)
#define UCON_TX_INTPOL_MODE (1<<2)
#define UCON_TX_DMA02_UART0 (2<<2)
#define UCON_TX_DMA13_UART1 (3<<2)
#define UCON_RX_MODE_DISABLE (0<<0)
#define UCON_RX_INTPOL_MODE (1<<0)
#define UCON_RX_DMA02_UART0 (2<<0)
#define UCON_RX_DMA13_UART1 (3<<0)
// UFCONn : UART FIFO CONTROL REGISTER
#define UFCON_TX_FIFO_TRG_EMPTY (0<<6)
#define UFCON_TX_FIFO_TRG_16BYTE (1<<6)
#define UFCON_TX_FIFO_TRG_32BYTE (2<<6)
#define UFCON_TX_FIFO_TRG_48BYTE (3<<6)
#define UFCON_RX_FIFO_TRG_1BYTE (0<<4)
#define UFCON_RX_FIFO_TRG_8BYTE (1<<4)
#define UFCON_RX_FIFO_TRG_16BYTE (2<<4)
#define UFCON_RX_FIFO_TRG_32BYTE (3<<4)
#define UFCON_TX_FIFO_RESET (1<<2)
#define UFCON_RX_FIFO_RESET (1<<1)
#define UFCON_FIFO_DISABLE (0<<0)
#define UFCON_FIFO_ENABLE (1<<0)
// UMCONn : UART MODEM CONTROL REGISTER
#define UMCON_AFC_DISABLE (0<<4)
#define UMCON_AFC_ENABLE (1<<4)
#define UMCON_RTS_HIGH_LVL (0<<0)
#define UMCON_RTS_LOW_LVL (1<<0)
// UTRSTATn : UART TX/RX/STATUS REGISTER
#define UTRSTAT_TRANSMITTER_EMPTY (1<<2)
#define UTRSTAT_TRANSMIT_BUF_EMPTY (1<<1)
#define UTRSTAT_RECEIVE_BUF_EMPTY (1<<0)
#define INREG(reg) (g_pComm1Reg->reg)
#define OUTREG( reg, value) (g_pComm1Reg->reg = value)
// set register by orring..
#define SETREG( reg, value) (g_pComm1Reg->reg |= value)
#define CLEARREG(reg, value) (g_pComm1Reg->reg &= ~value)
#define DisEnINT(pInfo, value) ( *(pInfo->UART_INTMASK) |= (value))
#define DisEnSubINT(pInfo, value) ( *(pInfo->UART_INTSUBMASK) |= (value))
#define EnINT(pInfo, value) ( *(pInfo->UART_INTMASK) &= ~(value))
#define EnSubINT(pInfo, value) ( *(pInfo->UART_INTSUBMASK) &= ~(value))
#define GetSubINTStatus(pInfo) ((*(pInfo->UART_INTSUBMASK)) & 0x1ff)
#define ClearINTPnd(pInfo, value) ( *(pInfo->UART_INTSRCPND) = (value))
#define ClearSubINTPnd(pInfo, value) ( *(pInfo->UART_INTSUBSRCPND) = (value))
//#define GetSubINTPndStatus(pInfo) (*(pInfo->UART_INTSUBSRCPND) & 0x1ff)
#define GetSubINTPndStatus(pInfo) 1
#define REG_POLL_LOOPS 2
#define REG_TIMEOUT_LOOPS 1000000
typedef enum {
STATE_INIT = 0,
STATE_GOT_BOF,
STATE_ACCEPTING,
STATE_ESC_SEQUENCE,
STATE_SAW_EOF,
STATE_CLEANUP
} portRcvState;
#define NDIS_IRDA_SPEED_2400 (UINT)(1 << 0) // SLOW IR ...
#define NDIS_IRDA_SPEED_9600 (UINT)(1 << 1)
#define NDIS_IRDA_SPEED_19200 (UINT)(1 << 2)
#define NDIS_IRDA_SPEED_38400 (UINT)(1 << 3)
#define NDIS_IRDA_SPEED_57600 (UINT)(1 << 4)
#define NDIS_IRDA_SPEED_115200 (UINT)(1 << 5)
#define NDIS_IRDA_SPEED_576K (UINT)(1 << 6) // MEDIUM IR ...
#define NDIS_IRDA_SPEED_1152K (UINT)(1 << 7)
#define NDIS_IRDA_SPEED_4M (UINT)(1 << 8) // FAST IR
typedef struct hwCapabilities {
/*
* This is a mask of NDIS_IRDA_SPEED_xxx bit values.
*
*/
UINT supportedSpeedsMask;
/*
* Time (in microseconds) that must transpire between
* a transmit and the next receive.
*/
UINT turnAroundTime_usec;
/*
* Extra BOF (Beginning Of Frame) characters required
* at the start of each received frame.
*/
UINT extraBOFsRequired;
} hwCapabilities;
/*
* This is the information that we need to keep for each COMM port.
*/
typedef struct {
/*
* HW resource settings for COM port.
*/
//
// Physical address of the ConfigIoBaseAddress
//
UINT ConfigIoBaseAddr;
//
// Physical address of the UartIoBaseAddress
//
UINT ioBase;
//
// Interrupt number this adapter is using.
//
UINT irq;
//
// DMA Cnannel Number.
//
UCHAR DMAChannel;
/*
* Is this COM port a 16550 with a 16-byte FIFO or
* a 16450/8250 with no FIFO ?
*/
BOOLEAN haveFIFO;
/*
* Data for our rcv state machine.
*/
UCHAR rawBuf[S24A0UART_FIFO_SIZE];
PUCHAR readBuf;
PUCHAR dmaReadBuf;
UINT readBufPos;
portRcvState rcvState;
//
// Debug counter for packets received correctly.
//
UINT PacketsReceived_DEBUG;
/*
* Data for send state machine
*/
PUCHAR writeBuf;
UINT writeBufPos;
UINT writeBufLen;
BOOLEAN writePending;
volatile unsigned int *UART_INTMASK;
volatile unsigned int *UART_INTSUBMASK;
volatile unsigned int *UART_INTPND;
volatile unsigned int *UART_INTSRCPND;
volatile unsigned int *UART_INTSUBSRCPND;
ULONG bINT;
ULONG bTxINT;
ULONG bRxINT;
ULONG bErrINT;
hwCapabilities hwCaps;
#if 0
/*
* Dongle or part-specific information
*/
dongleCapabilities hwCaps;
UINT dongleContext;
#endif
} comPortInfo;
extern USHORT comPortIOBase[];
#endif COMM_H
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