intr.c

来自「S3C24A0的完整BSP包,对开发此芯片的开发者很有用.」· C语言 代码 · 共 1,118 行 · 第 1/3 页

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  File: intr.c
//
//  This file implement major part of interrupt module for SMDK24A0 SoC.
//
#include <windows.h>
#include <ceddk.h>
#include <nkintr.h>
#include <oal.h>
#include <s3c24A0.h>
#include <s3c24A0_intr.h>
#include <intr.h>
#include <drv_glob.h>
#include <bsp.h>

#define DBG_ON 0

//------------------------------------------------------------------------------
//
//  Globals.

//  The global variables are storing virual address for interrupt and port
//  registers for use in interrupt handling to avoid possible time consumig
//  call to OALPAtoVA function.
//
static volatile S3C24A0_INTR_REG	*g_pIntrRegs; 
static volatile S3C24A0_IOPORT_REG	*g_pPortRegs;
static volatile S3C24A0_SDI_REG		*g_pSDIRegs; 
static volatile S3C24A0_PWM_REG		*g_pPWMRegs;
static volatile S3C24A0_ADC_REG		*g_pADCRegs;
static volatile S3C24A0_SDI_REG		*g_pSDIORegs;
static volatile S3C24A0_MEMSTICK_REG  *g_pMSRegs;
//  Function pointer to profiling timer ISR routine.
//
PFN_PROFILER_ISR g_pProfilerISR = NULL;

volatile IRDA_GLOBALS *pIrdaGloabls=&((DRIVER_GLOBALS *)DRIVER_GLOBALS_PHYSICAL_MEMORY_START)->irda;
//------------------------------------------------------------------------------
//
//  Function:  OALIntrInit
//
//  This function initialize interrupt mapping, hardware and call platform
//  specific initialization.
//
BOOL OALIntrInit()
{
	BOOL rc = FALSE;
    
	OALMSG( OAL_FUNC&&OAL_INTR, (L"+OALInterruptInit\r\n"));
	RETAILMSG(DBG_ON, (TEXT("In OALIntrInit++\r\n")));

	// Initialize interrupt mapping
	OALIntrMapInit();

	// First get uncached virtual addresses
	g_pIntrRegs		= (S3C24A0_INTR_REG*)OALPAtoVA(S3C24A0_BASE_REG_PA_INTR, FALSE);
	g_pPortRegs		= (S3C24A0_IOPORT_REG*)OALPAtoVA(S3C24A0_BASE_REG_PA_IOPORT, FALSE);
//	g_pSDIRegs		= (S3C24A0_SDI_REG*)OALPAtoVA(S3C24A0_BASE_REG_PA_SDI, FALSE);
	g_pPWMRegs	= (S3C24A0_PWM_REG*)OALPAtoVA(S3C24A0_BASE_REG_PA_PWM, FALSE);
	g_pADCRegs		= (S3C24A0_ADC_REG*)OALPAtoVA(S3C24A0_BASE_REG_PA_ADC, FALSE);
	g_pSDIORegs		= (S3C24A0_SDI_REG*)OALPAtoVA(S3C24A0_BASE_REG_PA_SDI, FALSE);
	g_pMSRegs		= (S3C24A0_MEMSTICK_REG*)OALPAtoVA(S3C24A0_BASE_REG_PA_MS, FALSE);
	// Mask and clear external interrupts
	g_pPortRegs->EINTMASK =  0xFFFFFFFF;
	g_pPortRegs->EINTPEND =  0xFFFFFFFF;

	// Mask and clear internal interrupts
	g_pIntrRegs->INTMSK = BIT_ALLMSK;
	if (g_pIntrRegs->SRCPND) 
		g_pIntrRegs->SRCPND =  BIT_ALLMSK;

	// Write the INTPND value itself to clear.
	if (g_pIntrRegs->INTPND) 
		g_pIntrRegs->INTPND = g_pIntrRegs->INTPND;

	// Mask and clear sub interrupt regs
	if (g_pIntrRegs->SUBSRCPND) 
		g_pIntrRegs->SUBSRCPND = BIT_SUB_ALLMSK;
	g_pIntrRegs->INTSUBMSK = BIT_SUB_ALLMSK;
	
#ifdef OAL_BSP_CALLBACKS
    // Give BSP change to initialize subordinate controller
	rc = BSPIntrInit();
#else
	rc = TRUE;
#endif

	OALMSG(OAL_INTR&&OAL_FUNC, (L"-OALIntrInit(rc = %d)\r\n", rc));
	return rc;
}


//------------------------------------------------------------------------------
//
//  Function:  OALIntrRequestIrqs
//
//  This function returns IRQs for CPU/SoC devices based on their
//  physical address.
//
BOOL OALIntrRequestIrqs(DEVICE_LOCATION *pDevLoc, UINT32 *pCount, UINT32 *pIrqs)
{
    BOOL rc = FALSE;

    OALMSG(OAL_INTR&&OAL_FUNC, (
        L"+OALIntrRequestIrqs(0x%08x->%d/%d/0x%08x/%d, 0x%08x, 0x%08x)\r\n",
        pDevLoc, pDevLoc->IfcType, pDevLoc->BusNumber, pDevLoc->LogicalLoc,
        pDevLoc->Pin, pCount, pIrqs
    ));

    // This shouldn't happen
    if (*pCount < 1) goto cleanUp;

#ifdef OAL_BSP_CALLBACKS
    rc = BSPIntrRequestIrqs(pDevLoc, pCount, pIrqs);
#endif    

cleanUp:        
    OALMSG(OAL_INTR&&OAL_FUNC, (L"-OALIntrRequestIrqs(rc = %d)\r\n", rc));
    return rc;
}


//------------------------------------------------------------------------------
//
//  Function:  OALIntrEnableIrqs
//
BOOL OALIntrEnableIrqs(UINT32 count, const UINT32 *pIrqs)
{
	UINT32 sysIntr = SYSINTR_NOP;
    BOOL rc = TRUE;
    UINT32 i, irq;
	
    //OALMSG(OAL_INTR&&OAL_FUNC, (L"+OALIntrEnableIrqs(%d, 0x%08x)\r\n", count, pIrqs));
	
	
    for (i = 0; i < count; i++) 
	{
#ifndef OAL_BSP_CALLBACKS
        irq = pIrqs[i];
#else
        // Give BSP chance to enable irq on subordinate interrupt controller
        irq = BSPIntrEnableIrq(pIrqs[i]);
#endif	
		
//		RETAILMSG(DBG_ON, (L"+OALIntrEnableIrqs(%d)\r\n", irq));
		INTERRUPTS_OFF();
		//TBDA change all sysintr to irq codes
		switch (irq) 
		{
		case IRQ_TIMER4:
			RETAILMSG(DBG_ON,(TEXT("OALIntrEnableIrqs:Timing\r\n")));
			// Clear the interrupt
			g_pIntrRegs->INTMSK &= ~( 1 << INTSRC_TIMER34);
			g_pIntrRegs->INTSUBMSK &= ~ (1 << INTSRC_TIMER34);			
			break;
				
		case IRQ_ADC:
			g_pIntrRegs->INTMSK &= ~BIT_ADC;
			g_pIntrRegs->INTSUBMSK &= ~(BIT_SUB_PENUP|BIT_SUB_PENDN);
			RETAILMSG(DBG_ON,(TEXT("OALIntrEnableIrqs:TOUCH\r\n")));
			break;
			
		case IRQ_TIMER1:
			RETAILMSG(DBG_ON,(TEXT("OALIntrEnableIrqs:TOUCH CHANGED\r\n")));			
			g_pIntrRegs->INTMSK &= ~BIT_TIMER1;
			
			break;
			
		case IRQ_SERIAL:	// Serial port.
			RETAILMSG(DBG_ON,(_T("OEMInterruptEnable:SERIAL uart0\r\n")));
			
			g_pIntrRegs->INTMSK    &= ~BIT_UART0;
			break;

		case IRQ_SIR:	// Serial irda port.
			RETAILMSG(DBG_ON,(_T("OEMInterruptEnable:SERIAL Uart1\r\n")));
			g_pIntrRegs->INTMSK    &= ~BIT_UART1;
			break;
		case IRQ_KEYPAD:
			RETAILMSG(DBG_ON,(_T("OALIntrEnableIrqs:KEYPAD\r\n")));
		  g_pIntrRegs->SRCPND = BIT_KEYPAD;
		  
		  if (g_pIntrRegs->INTPND & BIT_KEYPAD) 
		  	g_pIntrRegs->INTPND = BIT_KEYPAD;
		    g_pIntrRegs->INTMSK &= ~BIT_KEYPAD;
		    break;	
		case IRQ_MEMSTICK :
	    case IRQ_MEMSTICK_INSINT :
			g_pIntrRegs->INTSUBMSK &= ~(BIT_SUB_MSTICK);
			g_pIntrRegs->INTMSK &= ~BIT_IRDA_MSTICK;
			//RETAILMSG(DBG_ON,(TEXT("OALIntrEnableIrqs: Memory Stick\r\n")));
			break;    

		case IRQ_MEMSTICK_DMA:
			g_pIntrRegs->INTSUBMSK &= ~(BIT_SUB_DMA0);
			g_pIntrRegs->INTMSK &= ~BIT_DMA_SBUS;
			//RETAILMSG(DBG_ON,(TEXT("::: dwSysIntr_Memstick_DMA    OALIntrEnableIrqs\r\n")));
			break;
		case IRQ_USBD:
			g_pIntrRegs->SRCPND  = BIT_USBD;
			
			if (g_pIntrRegs->INTPND & BIT_USBD) 
				g_pIntrRegs->INTPND = BIT_USBD;

			g_pIntrRegs->INTMSK &= ~BIT_USBD;
			//RETAILMSG(DBG_ON,(_T("OALIntrEnableIrqs:USBD\r\n")));
			break;
		case IRQ_USBH:			// USB host.
			g_pIntrRegs->SRCPND  = BIT_USBH;
		
			if (g_pIntrRegs->INTPND & BIT_USBH) 
				g_pIntrRegs->INTPND = BIT_USBH;

			g_pIntrRegs->INTMSK &= ~BIT_USBH;
			//RETAILMSG(DBG_ON,(_T("OALIntrEnableIrqs:USBH\r\n")));
			break;
			

		case IRQ_SDMMC_SDIO_INTERRUPT:
			g_pIntrRegs->INTMSK &= ~BIT_MMC;
			RETAILMSG(DBG_ON,(TEXT("OEMInterruptEnable: IRQ_SDMMC_SDIO_INTERRUPT\r\n")));		
			break;
		case IRQ_SDDMA:
			g_pIntrRegs->INTSUBMSK &= ~(BIT_SUB_DMA3); //~(BIT_SUB_DMA2)
			g_pIntrRegs->INTMSK &= ~BIT_DMA_SBUS;
			//RETAILMSG(DBG_ON,(TEXT("OEMInterruptEnable: IRQ_SDDMA\r\n")));
			break;
		case IRQ_AUDIO:		// Audio controller (the controller uses both DMA0 and DMA1 interrupts).
			g_pIntrRegs->INTSUBMSK &= ~(BIT_SUB_DMA0|BIT_SUB_DMA2);
			g_pIntrRegs->INTMSK &= ~BIT_DMA_SBUS;			
			RETAILMSG(DBG_ON,(TEXT("OALIntrEnableIrqs:AUDIO\r\n")));
			break;

		case IRQ_CAMERA:
		    	g_pIntrRegs->INTMSK &= ~(BIT_CAMIF_C | BIT_CAMIF_P); // camera interrupt

			//RETAILMSG(DBG_ON,(TEXT("OALIntrEnableIrqs:IRQ_CAMERA 0x%X\r\n"), g_pIntrRegs->INTMSK));				
	   		break;

		case IRQ_IIC:
			//RETAILMSG(DBG_ON,(TEXT("OALIntrEnableIrqs:IRQ_IIC\r\n")));
			g_pIntrRegs->INTMSK &= ~BIT_IIC;
			break;

	       	
	    case IRQ_ETHER:			// Ethernet on EINT13.
			g_pPortRegs->EINTPEND   = (1<<13);
			g_pPortRegs->EINTMASK  &= ~(1<<13);
			g_pIntrRegs->SRCPND     = BIT_EINT11_14;	// by jylee
			
			if (g_pIntrRegs->INTPND & BIT_EINT11_14) 
				g_pIntrRegs->INTPND = BIT_EINT11_14;
			g_pIntrRegs->INTMSK    &= ~BIT_EINT11_14;
	//		RETAILMSG(1,(_T("OEMInterruptEnable:Ether\r\n")));
	        break;
		case IRQ_FIR:
			//RETAILMSG(1,(TEXT("OEMInterruptEnable:IRDA \r\n")));
			
	        if(pIrdaGloabls->bFIREnabled) {
			g_pIntrRegs->INTMSK &= ~BIT_IRDA_MSTICK;
			g_pIntrRegs->INTSUBMSK &= ~BIT_SUB_IRDA;

			    g_pIntrRegs->SUBSRCPND = BIT_SUB_DMA1; 
	           	g_pIntrRegs->INTSUBMSK &= ~(BIT_SUB_DMA1);
	           	g_pIntrRegs->SRCPND = (BIT_DMA_SBUS);

	    		if (g_pIntrRegs->INTPND & BIT_DMA_SBUS) 
		    		g_pIntrRegs->INTPND = BIT_DMA_SBUS;
	        	
	        	g_pIntrRegs->INTMSK &= ~BIT_DMA_SBUS;
	        }else {
	    		g_pIntrRegs->SUBSRCPND  = (INTSUB_RXD1 | INTSUB_TXD1 | INTSUB_ERR1);
	    		g_pIntrRegs->INTSUBMSK &= ~INTSUB_RXD1;
	            //	    g_pIntrRegs->INTSUBMSK &= ~INTSUB_TXD1;
	            //		g_pIntrRegs->INTSUBMSK &= ~INTSUB_ERR1;
	    		g_pIntrRegs->SRCPND     = BIT_UART1;
	    		// S3C24A0X Developer Notice (page 4) warns against writing a 1 to a 0 bit in the INTPND register.
			    if (g_pIntrRegs->INTPND & BIT_UART1) g_pIntrRegs->INTPND = BIT_UART1;
	    		g_pIntrRegs->INTMSK    &= ~BIT_UART1;
	        }	
			//RETAILMSG(1,(TEXT("OEMInterruptEnable:Done\r\n")));        	
			break;

		default:
			RETAILMSG(DBG_ON,(TEXT("OALIntrEnableIrqs:Unsupported %d\r\n"),irq));
			rc = FALSE;	/* unsupported interrupt value */
			break;
		}
	
	}
    
	INTERRUPTS_ON(); // what is this!!
    
    //OALMSG(OAL_INTR&&OAL_FUNC, (L"-OALIntrEnableIrqs(rc = %d)\r\n", rc));
    return rc;    
}


//------------------------------------------------------------------------------
//
//  Function:  OALIntrDisableIrqs
//
VOID OALIntrDisableIrqs(UINT32 count, const UINT32 *pIrqs)
{
    UINT32 i, irq;
	
//    OALMSG(OAL_INTR&&OAL_FUNC, (
  //      L"+OALIntrDisableIrqs(%d, 0x%08x)\r\n", count, pIrqs
	//	));
	
    for (i = 0; i < count; i++) 
	{
#ifndef OAL_BSP_CALLBACKS
        irq = pIrqs[i];
#else
        // Give BSP chance to disable irq on subordinate interrupt controller
        irq = BSPIntrDisableIrq(pIrqs[i]);
        if (irq == OAL_INTR_IRQ_UNDEFINED) continue;
#endif
        INTERRUPTS_OFF();
		
		switch (irq) 
		{
		case IRQ_TIMER1:
			RETAILMSG(DBG_ON,(TEXT("OEMInterruptDisable:TOUCH CHANGED \r\n\r\n")));
			break;
			
		case IRQ_ADC:
			g_pIntrRegs->INTMSK |= BIT_ADC;
			g_pIntrRegs->INTSUBMSK |= (BIT_SUB_PENUP|BIT_SUB_PENDN);
			RETAILMSG(DBG_ON,(TEXT("OEMInterruptDisable:TOUCH \r\n\r\n")));
			break;
		case IRQ_USBH:
			g_pIntrRegs->INTMSK |= BIT_USBH;
			//RETAILMSG(DBG_ON,(_T("OALIntrDisableIrqs:USBH\r\n")));
			break;
		case IRQ_AUDIO:
			g_pIntrRegs->INTMSK |= BIT_DMA_SBUS;
			g_pIntrRegs->INTSUBMSK |= (BIT_SUB_DMA0|BIT_SUB_DMA2);
			RETAILMSG(DBG_ON,(TEXT("OALIntrDisableIrqs:AUDIO\r\n\r\n")));
			break;
			
		case IRQ_SERIAL:
			g_pIntrRegs->INTMSK    |= BIT_UART0;
			RETAILMSG(DBG_ON,(TEXT("OEMInterruptDisable:UART0 \r\n")));			
			break;
			
		case IRQ_SIR:
			g_pIntrRegs->INTMSK    |= BIT_UART1;
			RETAILMSG(DBG_ON,(TEXT("OEMInterruptDisable:UART1 \r\n")));			
			break;
		case IRQ_KEYPAD:
			//RETAILMSG(1,(_T("OEMInterruptDisable:KEYPAD\r\n")));
		   g_pIntrRegs->INTMSK |= BIT_KEYPAD;
           break;	

		case IRQ_MEMSTICK :
	    case IRQ_MEMSTICK_INSINT :
	
//	case SYSINTR_MEMSTICK_PROTOCOMPLETE:
//	case SYSINTR_MEMSTICK_SIFINTREVENT: