mac.h

嵌入式linux（arm9）的平台下

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 *
 * Copyright:
 *	Advanced Micro Devices, AMD. All Rights Reserved.  
 *  You are hereby granted a copyright license to use, modify, and
 *  distribute the SOFTWARE so long as this entire notice is
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 *  software is provided on an "AS IS" basis and without warranty.
 *
 *  To the maximum extent permitted by applicable law, AMD 
 *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING 
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 *  of this software.
 *********************************************************************
 *
 * File:		MAC.h
 *
 * Purpose:		Definitions for Au1550 Ethernet MACs
 *
 *  $RCSfile: MAC.h,v $
 *  $Author: fredb $
 *  $Revision: 1.1 $
 *  $Date: 2003/11/25 23:05:09 $			 
 *
***********************************************************************/
 

#ifndef _AU1550__MAC_H
#define _AU1550__MAC_H

#define _AU1500

  // MAC0, MAC1  Controller Definition

	/*MAC Physical Base Addresses*/

#define MAC0_BASE_ADDRESS	 (0x10500000)
#define MAC1_BASE_ADDRESS	 (0x10510000)
	
	/*MAC Enable Physical Base Addresses*/

#define MAC0EN_BASE_ADDRESS	 (0x10520000)
#define MAC1EN_BASE_ADDRESS	 (0x10520004)
 
   /*MAC DMA Physical Base Addresses*/

#define MACDMA0_BASE_ADDRESS (0x14004000)
#define MACDMA1_BASE_ADDRESS (0x14004200)
#define KSEG1(addr) (addr | (0xA <<28))

//===================================================
//   - AU1550 has the different base Addresses

#ifdef AU1500

#undef MAC0_BASE_ADDRESS
#undef MAC1_BASE_ADDRESS
#undef MAC0EN_BASE_ADDRESS
#undef MAC1EN_BASE_ADDRESS 
#undef MACDMA0_BASE_ADDRESS 
#undef MACDMA1_BASE_ADDRESS


#define MAC0_BASE_ADDRESS	 (0x11500000)
#define MAC1_BASE_ADDRESS	 (0x11510000)
	
	/*MAC Enable Physical Base Addresses*/

#define MAC0EN_BASE_ADDRESS	 (0x11520000)
#define MAC1EN_BASE_ADDRESS	 (0x11520004)
 
   /*MAC DMA Physical Base Addresses*/

#define MACDMA0_BASE_ADDRESS (0x14004000)
#define MACDMA1_BASE_ADDRESS (0x14004200)

#endif

//===================================================

	/*MAC Registers*/

#define MAC_CONTROL 		0x0000
#define MAC_ADDRHIGH		0x0004
#define MAC_ADDRLOW 		0x0008
#define MAC_HASHHIGH		0x000C
#define MAC_HASHLOW 		0x0010
#define MAC_MIICTRL 		0x0014
#define MAC_MIIDATA 		0x0018
#define MAC_FLOWCTRL		0x001C
#define MAC_VLAN1			0x0020
#define MAC_VLAN2			0x0024

typedef volatile struct
{
unsigned long mac_ctrl;   // Operation Mode and Address Filter 
unsigned long mac_add_high;  // High 16 bits of the MAC Physical Address 
unsigned long mac_add_low;   // Lower 32 bits of the MAC Physical Address 
unsigned long mac_hash_high;  // High 32 bits of the Multicast Hash Address 
unsigned long mac_hash_low;   // LOW 32 bits of the Multicast Hash Address 
unsigned long mac_mii_ctrl;   // Control of PHY Management Interface 
unsigned long mac_mii_data;   // Data to be writen to or read from PHY 
unsigned long mac_flow_ctrl;  // Control frame generation 
unsigned long mac_vlan_1;     // VLAN1 tag 
unsigned long mac_vlan_2;     // VLAN2 tag 
}MAC_REGISTERS;



/*
 * Bit definitions for MAC Control Register at offset= 0x0000
 */

 //	Reserved bits are zeroed
   
#define MAC_CONTROL_RSV    (0xC0FFBDEC)

//	Receiver Enable
#define MAC_CONTROL_RE	  	   (1<<2)

//	Transmitter Enable
#define MAC_CONTROL_TE	  	   (1<<3)

//	Deferral Check
#define MAC_CONTROL_DC		   (1<<5)

//	Back Off Limit
#define MAC_CONTROL_BL		   (3<<6)

enum { SLOT_TIME=0,  // 00 = 1 slot time
 	   SLOT_TIME2,   // 01 = 2 slot time
	   SLOT_TIME3,   // 10 = 3 slot time
	   SLOT_TIME4,   // 11 = 4 slot time
};
//	Automatic Pad Stripping
#define MAC_CONTROL_AP		   (1<<8)

//	Disable Retry
#define MAC_CONTROL_DR  	   (1<<10)

//	Disable Broadcast Frames
#define MAC_CONTROL_DB		   (1<<11)

//	Late Collision Control
#define MAC_CONTROL_LC		   (1<<12)

//Hash/Perfect Filtering Mode
#define MAC_CONTROL_HP  	   (1<<13)

//	Hash Only Filtering mode
#define MAC_CONTROL_HO		   (1<<15)

//Pass Bad Frame
#define MAC_CONTROL_PB		   (1<<16)
//Inverse Filtering

#define MAC_CONTROL_IF  	   (1<<17)
//	Promiscuous Mode

#define MAC_CONTROL_PR		   (1<<18)

//	Pass All Multicast
#define MAC_CONTROL_PM  	   (1<<19)

//	Full Duplex Mode
#define MAC_CONTROL_F   	   (1<<20)

//	Loopback Operating Mode
#define MAC_C0NTROL_LM		   (3<<21)

enum { NORMAL_MODE=0,  // 00 =  Normal Mode
 	   LOOP_INT,	     // 01 = Internal Loopback
	   LOOP_EXT,	     // 10 = External Loopback
	   RSVD	          // 11 = Reserved
};


//	Disable Receive Own
#define MAC_CONTROL_DO		   (1<<23)

//	Endian Mode for Data buffers
#define MAC_CONTROL_EM		   (1<<30)

//	Receive All
#define MAC_CONTROL_RA		   (1<<31)

/*
 * Bit definitions for MAC_MIIControl Registers at offset= 0x0014
 */
 
 //	Reserved bits are zeroed
   
#define MAC_MIICTRL_RSV    (0x0000FFC3)

//	MII Busy
#define MAC_MIICTRL_MB	    	   (1<<0)

//	MII Write
#define MAC_MIICTRL_MW	  	       (1<<1)

//	MII Register
#define MAC_MIICTRL_MIIREG	        (1F<<6)

//	PHY Address
#define MAC_MIICTRL_PHYADDR	        (1F<<11)

  /*
 * Bit definitions for MAC_Flow Control Registers at offset= 0x001C
 */
 
 //	Reserved bits are zeroed
   
#define MAC_FLOWCTRL_RSV    (0xFFFF0007)

//	Flow control Busy Status
#define MAC_FLOWCTRL_FB	    	   (1<<0)

//	Flow Control Enable
#define MAC_FLOWCTRL_FE	  	       (1<<1)

//	Pass Control Frame
#define MAC_FLOWCTRL_PC	           (1<<2)

//	Pause Time
#define MAC_FLOWCTRL_PT              (FFFF<<16)

  /*
 * Bit definitions for MAC Enable Registers at offset=0X0000
 * Offset from MAC Enable Physical Base Addresses
 */
 
 //	Reserved bits are zeroed
   
#define MACEN_MAC0_RSV    (0x0000007F)

//	Clock Enable
#define MACEN_MAC0_CE	    	   (1<<0)

//	Enable Field bit 0
#define MACEN_MAC0_TS	  	       (1<<1)

//	Coherent/Non coherent Memory accesses
#define MACEN_MAC0_C	           (1<<3)

//	Enable field bits 2 and 1 . Together with bit enable bit 0
// This field resets and enables the MAC
#define MACEN_MAC0_E21              (3<<4)
    
enum { RESET= 0,  // 000 =  Reset
 	   ENABLE,	  // 111 = Internal Loopback
	  };
  
//	Jumbo Packet
#define MACEN_MAC0_JP	           (1<<6)

  
 	// MAC Receive Status bit Definitions

#define MAC_LENGTH				 	(3FFF<<0)
	
#define MAC_WT						(1<<14)

#define MAC_RF						(1<<15)

#define MAC_FL						(1<<16)

#define MAC_CS						(1<<17)
 
#define MAC_FT  					(1<<18)

#define MAC_ME						(1<<19)

#define MAC_DB						(1<<20)

#define MAC_CR						(1<<21)

#define MAC_V1						(1<<22)

#define MAC_V2						(1<<23)

#define MAC_LE  					(1<<24)

#define MAC_CF						(1<<25)

#define MAC_UC  					(1<<26)

#define MAC_MF   					(1<<27)

#define MAC_BF  					(1<<28)

#define MAC_FF						(1<<29)

#define MAC_PF						(1<<30)

#define MAC_MI						(1<<31)

   
   // MAC Receive Buffer Start Address/ Enable Register bit Definitions
   //	Reserved bits are zeroed
   
#define MAC_RXADDR_RSV    (0xFFFFFFEF)

#define MAC_REN						(1<<0)
#define MAC_RDN						(1<<1)
#define MAC_RCB    			 	    (1<<2)
#define MAC_ADDDR			    	(7FFFFFF<<5)

	// MAC Transmit Packet Status bit Definitions
#define MAC_TXADDR_RSV    (0x100003FFF)

#define MAC_FA  				 	(1<<0)	
#define MAC_JT						(1<<1)
#define MAC_NC						(1<<2)
#define MAC_LS						(1<<3)
#define MAC_ED						(1<<4) 
#define MAC_LC  					(1<<5)
#define MAC_EC						(1<<6)
#define MAC_UR						(1<<7)
#define MAC_DF  					(1<<8)
#define MAC_LO						(1<<9)
#define MAC_CC						(F<<10)
#define MAC_PR  					(1<<31)

   // MAC Transmit Buffer Start Address/ Enable Register bit Definitions
#define MAC_TXBUF_ADDR_RSV    (0xFFFFFFEF)

#define MAC_TXBUF_EN						(1<<0)
#define MAC_TXBUF_DN						(1<<1)
#define MAC_TXBUF_CB    			 	    (3<<2)
#define MAC_TXBUF_ADDDR		    	    	(7FFFFFF<<5)
  

     // MAC Transmit Buffer Length Register bit Definitions
#define MAC_TXBUFL_RSV    (0x00003FFF)

#define MAC_TXBUFL_LEN						(3FFF<<0)




	   // MAC DMA Setup


	#endif