psc.h

嵌入式linux（arm9）的平台下

#define	PSC_I2S_EVNT_TR			(1<<10)		// TX Fifo request
#define	PSC_I2S_EVNT_RU			(1<<11)		// RX Fifo underflow
#define	PSC_I2S_EVNT_RO			(1<<12)		// RX fifo overflow
#define	PSC_I2S_EVNT_RR			(1<<13)		// RX Fifo request

#define PSC_I2S_TXRX_DATA		(0xFFFFFF<<0)	// Data
#define PSC_I2S_TXRX_DATA_N(n)	((n&0xFFFFFF)<<0)

/*
################################################################################################
#####                         AC97 Register Definitions                                    #####
################################################################################################
*/

#define PSC_AC97_SEL	 	PSC_SEL
#define PSC_AC97_CTL	 	PSC_CTL
#define PSC_AC97_CFG	 	0x00000008
#define PSC_AC97_MSK	 	0x0000000C
#define PSC_AC97_PCR	 	0x00000010
#define PSC_AC97_STS	 	0x00000014
#define PSC_AC97_EVNT	 	0x00000018
#define PSC_AC97_TXRX	 	0x0000001C
#define PSC_AC97_CDC		0x00000020
#define PSC_AC97_RST		0x00000024
#define PSC_AC97_GPO		0x00000028
#define PSC_AC97_GPI		0x0000002C

#ifndef ASSEMBLER
typedef volatile struct
{
	PSC_SELECT	psc;		//00,04
	uint32		cfg;		//08
	uint32		msk;		//0C
	uint32		pcr;		//10
	uint32		sts;		//14
	uint32		evnt;		//18
	uint32		txrx;		//1C
	uint32		cdc;		//20
	uint32		rst;		//24
	uint32		gpo;		//28
	uint32		gpi;		//2C
} PSC_AC97;
#endif

#define PSC_AC97_CFG_GE			(1<<0)		// GPIO Register Enable
#define PSC_AC97_CFG_RXSLOT		(0x3FF<<1)	// Valid Rx slots
#define PSC_AC97_CFG_RXSLOT_N(n) ((n&0x3FF)<<1)	
#define PSC_AC97_CFG_TXSLOT		(0x3FF<<11)	// Valid Tx slots
#define PSC_AC97_CFG_TXSLOT_N(n) ((n&0x3FF)<<11)	
#define PSC_AC97_CFG_LEN		(0x1F<<21)	// Data Length
#define PSC_AC97_CFG_LEN_N(n) ((n&0x1F)<<21)	
#define PSC_AC97_CFG_DE			(1<<26)		// Device Enable
#define PSC_AC97_CFG_DD			(1<<27)		// DMA Disable
#define	PSC_AC97_CFG_TRD	  	(0x3<<28)	// TX Request Depth
#define	PSC_AC97_CFG_TRD_N(n)	((n&0x3)<<28)
#define	PSC_AC97_CFG_RRD	  	(0x3<<30)	// Rx Request Depth
#define	PSC_AC97_CFG_RRD_N(n)	((n&0x3)<<30)

#define	PSC_AC97_MSK_TD			(1<<4)		// Tx Done
#define	PSC_AC97_MSK_RD			(1<<5)		// Rx Done
#define	PSC_AC97_MSK_TU			(1<<8)		// TX Fifo underflow
#define	PSC_AC97_MSK_TO			(1<<9)		// TX fifo overflow
#define	PSC_AC97_MSK_TR			(1<<10)		// TX Fifo request
#define	PSC_AC97_MSK_RU			(1<<11)		// RX Fifo underflow
#define	PSC_AC97_MSK_RO			(1<<12)		// RX fifo overflow
#define	PSC_AC97_MSK_RR			(1<<13)		// RX Fifo request
#define	PSC_AC97_MSK_CD			(1<<24)		// CODEC Command done
#define	PSC_AC97_MSK_GR			(1<<25)		// GPI Data Ready Interrupt

#define PSC_AC97_PCR_TS			(1<<0)		// Tx start
#define PSC_AC97_PCR_TP			(1<<1)		// Tx Stop
#define PSC_AC97_PCR_TC			(1<<2)		// Tx Data Clear
#define PSC_AC97_PCR_RS			(1<<4)		// Rx Start
#define PSC_AC97_PCR_RP			(1<<5)		// Rx Stop
#define PSC_AC97_PCR_RC			(1<<6)		// Rx Data Clear

// Status Register is Read Only //
#define PSC_AC97_STS_SR			(1<<0)		// PSC Ready
#define PSC_AC97_STS_DR			(1<<1) 		// Device Ready	
#define PSC_AC97_STS_DI			(1<<2)		// Device INterrupt
#define PSC_AC97_STS_TB			(1<<4)		// Tx BUsy
#define PSC_AC97_STS_RB			(1<<5)		// Rx Busy
#define PSC_AC97_STS_TR			(1<<8)		// Tx Rrequest
#define PSC_AC97_STS_TE			(1<<9)		// Tx Fifo Empty
#define PSC_AC97_STS_TF			(1<<10)		// Tx Fifo Full
#define PSC_AC97_STS_RR			(1<<11)		// Rx Rrequest
#define PSC_AC97_STS_RE			(1<<12)		// Rx Fifo Empty
#define PSC_AC97_STS_RF			(1<<13)		// Rx Fifo Full
#define PSC_AC97_STS_CR			(1<<24)		// Codec ready
#define PSC_AC97_STS_CP			(1<<25)		// Command Pending
#define PSC_AC97_STS_CB			(1<<26)		// Codec Bit Clock detected

#define	PSC_AC97_EVNT_TD   		(1<<4)		// Tx Done
#define	PSC_AC97_EVNT_RD   		(1<<5)		// Rx Done
#define	PSC_AC97_EVNT_TU   		(1<<8)		// TX Fifo underflow
#define	PSC_AC97_EVNT_TO   		(1<<9)		// TX fifo overflow
#define	PSC_AC97_EVNT_TR   		(1<<10)		// TX Fifo request
#define	PSC_AC97_EVNT_RU   		(1<<11)		// RX Fifo underflow
#define	PSC_AC97_EVNT_RO   		(1<<12)		// RX fifo overflow
#define	PSC_AC97_EVNT_RR   		(1<<13)		// RX Fifo request
#define	PSC_AC97_EVNT_CD   		(1<<24)		// CODEC Command done
#define	PSC_AC97_EVNT_GR   		(1<<25)		// GPI Data Ready Interrupt

#define PSC_AC97_TXRX_DATA		(0xFFFFF<<0)	// Data
#define PSC_AC97_TXRX_DATA_N(n)	((n&0xFFFFF)<<0)

#define PSC_AC97_CDC_DATA		(0xFFFF<<0)	// data
#define PSC_AC97_CDC_DATA_N(n) 	((n&0xFFFF)<<0)
#define PSC_AC97_CDC_INDX		(0x7F<<16)	// register index
#define PSC_AC97_CDC_INDX_N(n) 	((n&0x7F)<<16)
#define PSC_AC97_CDC_ID			(0x3<<23)	// 2bit id for codec
#define PSC_AC97_CDC_ID_N(n) 	((n&0x3)<<23)
#define PSC_AC97_CDC_RD			(1<<25)		// Codec Read/Write

#define PSC_AC97_RST_SNC		(1<<0)		// Sync signal control
#define PSC_AC97_RST_RST		(1<<1)		// AC link reset

#define PSC_AC97_GPO_DATA		(0xFFFFF<<0)
#define PSC_AC97_GPO_DATA_N(n)	((n&0xFFFFF)<<0)

#define PSC_AC97_GPI_DATA		(0xFFFFF<<0)
#define PSC_AC97_GPI_DATA_N(n)	((n&0xFFFFF)<<0)


/*
################################################################################################
#####                        SMBus Register Definitions                                    #####
################################################################################################
*/

#define PSC_SMB_SEL	 		PSC_SEL
#define PSC_SMB_CTL	 		PSC_CTL
#define PSC_SMB_CFG	 		0x00000008
#define PSC_SMB_MSK	 		0x0000000C
#define PSC_SMB_PCR	 		0x00000010
#define PSC_SMB_STS	 		0x00000014
#define PSC_SMB_EVNT	 	0x00000018
#define PSC_SMB_TXRX	 	0x0000001C
#define PSC_SMB_TMR			0x00000030

#ifndef ASSEMBLER
typedef volatile struct
{
	PSC_SELECT	psc;		//00,04
	uint32		cfg;		//08
	uint32		msk;		//0C
	uint32		pcr;		//10
	uint32		sts;		//14
	uint32		evnt;		//18
	uint32		txrx;		//1C
	uint32		tmr;		//20
} PSC_SMB;
#endif

#define PSC_SMB_CFG_SLV			(0x7F<<4)	// Slave Address
#define PSC_SMB_CFG_SLV_N(n)	((n&0x7F)<<1)	
#define PSC_SMB_CFG_SFM			(1<<8)		// Standard or Fast Mode
#define PSC_SMB_CFG_CGE			(1<<9)		// General Call Enable
#define	PSC_SMB_CFG_SDIV		(0x3<<13)	// Clock Divider
#define	PSC_SMB_CFG_SDIV_N(n)	((n&0x3)<<13)
#define PSC_SMB_CFG_DE			(1<<26)		// Device Enable
#define PSC_SMB_CFG_DD			(1<<27)		// DMA Disable
#define	PSC_SMB_CFG_TRD			(0x3<<28)	// TX Request Depth
#define	PSC_SMB_CFG_TRD_N(n)	((n&0x3)<<28)
#define	PSC_SMB_CFG_RRD			(0x3<<30)	// Rx Request Depth
#define	PSC_SMB_CFG_RRD_N(n)	((n&0x3)<<30)


#define	PSC_SMB_MSK_MD			(1<<4)		// Master Done
#define	PSC_SMB_MSK_SD			(1<<5)		// Slave done
#define	PSC_SMB_MSK_TU			(1<<8)		// TX Fifo underflow
#define	PSC_SMB_MSK_TO			(1<<9)		// TX fifo overflow
#define	PSC_SMB_MSK_RU			(1<<11)		// RX Fifo underflow
#define	PSC_SMB_MSK_RO			(1<<12)		// RX fifo overflow
#define	PSC_SMB_MSK_MM			(1<<16)		// Multiple Master Error
#define	PSC_SMB_MSK_AL			(1<<28)		// Arbitration Lost (MasterOnly)
#define	PSC_SMB_MSK_AN			(1<<29)		// Address not ack'd
#define	PSC_SMB_MSK_DN			(1<<30)		// Data nont ack'd

#define PSC_SMB_PCR_MS			(1<<0)		// Master Start
#define PSC_SMB_PCR_DC			(1<<2)		// Tx Data Clear

// Status Register is Read Only //
#define PSC_SMB_STS_SR			(1<<0)		// PSC Ready
#define PSC_SMB_STS_DR			(1<<1) 		// Device Ready	
#define PSC_SMB_STS_DI			(1<<2)		// Device INterrupt
#define PSC_SMB_STS_MB			(1<<4)		// Master BUsy
#define PSC_SMB_STS_SB			(1<<5)		// Slave Busy
#define PSC_SMB_STS_TR			(1<<8)	 	// Tx Rrequest
#define PSC_SMB_STS_TE			(1<<9)		// Tx Fifo Empty
#define PSC_SMB_STS_TF			(1<<10)		// Tx Fifo Full
#define PSC_SMB_STS_RR			(1<<11)		// Rx Rrequest
#define PSC_SMB_STS_RE			(1<<12)		// Rx Fifo Empty
#define PSC_SMB_STS_RF			(1<<13)		// Rx Fifo Full
#define PSC_SMB_STS_BB			(1<<28)		// Bus Busy

#define	PSC_SMB_EVNT_MD			(1<<4)		// Master Done
#define	PSC_SMB_EVNT_SD			(1<<5)		// Slave done
#define	PSC_SMB_EVNT_TU			(1<<8)		// TX Fifo underflow
#define	PSC_SMB_EVNT_TO			(1<<9)		// TX fifo overflow
#define	PSC_SMB_EVNT_RU			(1<<11)		// RX Fifo underflow
#define	PSC_SMB_EVNT_RO			(1<<12)		// RX fifo overflow
#define	PSC_SMB_EVNT_MM			(1<<16)		// Multiple Master Error
#define	PSC_SMB_EVNT_AL			(1<<28)		// Arbitration Lost (MasterOnly)
#define	PSC_SMB_EVNT_AN			(1<<29)		// Address not ack'd
#define	PSC_SMB_EVNT_DN			(1<<30)		// Data nont ack'd

#define PSC_SMB_TXRX_AD			(0xFF<<0)	// Addr/Data
#define PSC_SMB_TXRX_AD_N(n)	((n&0xFF)<<0)
#define PSC_SMB_TXRX_STP		(1<<29)		// Stop
#define PSC_SMB_TXRX_RSR		(1<<30)		// Restart

#define PSC_SMB_TMR_CH			(0x1F<<0)	// Clock High
#define PSC_SMB_TMR_CH_N(n)		((n&0x1F)<<0)
#define PSC_SMB_TMR_CL			(0x1F<<5)	// Clock Low
#define PSC_SMB_TMR_CL_N(n)		((n&0x1F)<<5)
#define PSC_SMB_TMR_SU			(0x1F<<10)	// Start Setup 
#define PSC_SMB_TMR_SU_N(n)		((n&0x1F)<<10)
#define PSC_SMB_TMR_SH			(0x1F<<15)	// Start Hold
#define PSC_SMB_TMR_SH_N(n)		((n&0x1F)<<15)
#define PSC_SMB_TMR_PU			(0x1F<<20)	// Stop Setup
#define PSC_SMB_TMR_PU_N(n)		((n&0x1F)<<20)
#define PSC_SMB_TMR_PS			(0x1F<<25)	// Stop Start Buffer
#define PSC_SMB_TMR_PS_N(n)		((n&0x1F)<<25)
#define PSC_SMB_TMR_TH			(0x3<<30)	// Transmit Hold
#define PSC_SMB_TMR_TH_N(n)		((n&0x3)<<30)


static inline void psc_config( uint32 psc, uint32 type )
{
	PSC_SELECT		*psc_sel = (PSC_SELECT*)KSEG1(psc);
	psc_sel->sel = type;
} 

static inline void psc_enable( uint32 psc, uint32 clk_src )
{
	PSC_SELECT		*psc_sel = (PSC_SELECT*)KSEG1(psc);
	PSC_SPI 		*spi;

	psc_sel->ctl |= PSC_CTL_CE;	
	asm(" sync");
	psc_sel->ctl |= PSC_CTL_EN;	
	asm(" sync");
	
	// Going to cheat a little here -- since the device ready bit is the same for
	// all available PSC configurations -- I will just use SPI data structure to 
	// poll for "device ready". NOTE -- not all the status bits are the same
	// for the different configurations
	spi = (PSC_SPI*)psc_sel;
	while ( !(spi->sts & PSC_SMB_STS_SR) ) ;;

}

static inline void psc_disable( uint32 psc )
{
	PSC_SELECT		*psc_sel = (PSC_SELECT*)KSEG1(psc);
	psc_sel->ctl &= ~PSC_CTL_EN;
	asm(" sync");	
	psc_sel->ctl &= ~PSC_CTL_CE;	
	asm(" sync");	
}
#endif // __AU1550_PSC_H_