psc.h

嵌入式linux（arm9）的平台下

/*********************************************************************
 *
 * Copyright:
 *	Advanced Micro Devices, AMD. All Rights Reserved.  
 *  You are hereby granted a copyright license to use, modify, and
 *  distribute the SOFTWARE so long as this entire notice is
 *  retained without alteration in any modified and/or redistributed
 *  versions, and that such modified versions are clearly identified
 *  as such. No licenses are granted by implication, estoppel or
 *  otherwise under any patents or trademarks of AMD. This 
 *  software is provided on an "AS IS" basis and without warranty.
 *
 *  To the maximum extent permitted by applicable law, AMD 
 *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING 
 *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
 *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE 
 *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY 
 *  ACCOMPANYING WRITTEN MATERIALS.
 * 
 *  To the maximum extent permitted by applicable law, IN NO EVENT
 *  SHALL AMD BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING 
 *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS 
 *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
 *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.   
 * 
 *  AMD assumes no responsibility for the maintenance and support
 *  of this software.
 *********************************************************************
 *
 * File:		psc.h
 *
 * Purpose:		Definitions for Au1550 PSC
 *
 *  $RCSfile: psc.h,v $
 *  $Author: cgray $
 *  $Revision: 1.6 $
 *  $Date: 2003/12/22 21:14:11 $
 *
***********************************************************************/
#ifndef __AU1550_PSC_H_
#define __AU1550_PSC_H_

#define AU1500_NUM_PSC			4

#define PSC0_PHYS_ADDRESS 		0x11A00000
#define PSC1_PHYS_ADDRESS 		0x11B00000
#define PSC2_PHYS_ADDRESS 		0x10A00000
#define PSC3_PHYS_ADDRESS 		0x10B00000

#define PSC0					PSC0_PHYS_ADDRESS
#define PSC1					PSC1_PHYS_ADDRESS
#define PSC2					PSC2_PHYS_ADDRESS
#define PSC3					PSC3_PHYS_ADDRESS

#define PSC_SEL					0x00000000
#define PSC_CTL					0x00000004

#ifndef ASSEMBLER
typedef volatile struct
{
	uint32 	sel;							// PSC Select
	uint32	ctl;							// PSC control
} PSC_SELECT;
#endif

#define	PSC_SEL_PS				(0x7<<0)	// Protocol select
#define PSC_SEL_PS_N(n)			((n&0x7)<<0)
#define	PSC_SEL_CLK				(0x3<<4)	// Clock Source
#define PSC_SEL_CLK_N(n) 		((n&0x3)<<4)
#define PSC_SEL_CLK_TOY			PSC_SEL_CLK_N(0)
#define PSC_SEL_CLK_OFFCHIP		PSC_SEL_CLK_N(1)
#define PSC_SEL_CLK_SERIAL		PSC_SEL_CLK_N(2)
#define PSC_CTL_CE				(1<<0)		// Clock Enable
#define PSC_CTL_EN				(1<<1)		// PSC Enable

#define PSC_SEL_PS_SPI			(PSC_SEL_PS_N(2))
#define PSC_SEL_PS_I2S			(PSC_SEL_PS_N(3))
#define PSC_SEL_PS_AC97			(PSC_SEL_PS_N(4))
#define PSC_SEL_PS_SMB			(PSC_SEL_PS_N(5))

/*
 *	Some simple defines for passing to functions
 */
#define _PSC_SPI 				PSC_SEL_PS_SPI
#define _PSC_I2S			  	PSC_SEL_PS_I2S
#define _PSC_AC97			  	PSC_SEL_PS_AC97
#define _PSC_SMB				PSC_SEL_PS_SMB


/*
################################################################################################
#####                         SPI  Register Definitions                                    #####
################################################################################################
*/

#define PSC_SPI_SEL			PSC_SEL
#define PSC_SPI_CTL			PSC_CTL
#define PSC_SPI_CFG			0x00000008
#define PSC_SPI_MSK			0x0000000C
#define PSC_SPI_PCR			0x00000010
#define PSC_SPI_STS			0x00000014
#define PSC_SPI_EVNT		0x00000018
#define PSC_SPI_TXRX		0x0000001C

#ifndef ASSEMBLER
typedef volatile struct
{
	PSC_SELECT	psc;		//00,04
	uint32		cfg;		//08
	uint32		msk;		//0C
	uint32		pcr;		//10
	uint32		sts;		//14
	uint32		evnt;		//18
	uint32		txrx;		//1C
} PSC_SPI;
#endif

#define PSC_SPI_CFG_MO			(1<<0)		// Master Only Mode
#define PSC_SPI_CFG_MLF			(1<<1)		// MSB/LSB Data First
#define PSC_SPI_CFG_LB			(1<<3)		// Loopback mode
#define PSC_SPI_CFG_LEN			(0x1F<<4)	// Length mask
#define PSC_SPI_CFG_LEN_N(n)	((n&0x1F)<<4)	// Length 'n'
#define PSC_SPI_CFG_CDE			(1<<9)		// Clock Phase Delay
#define	PSC_SPI_CFG_CCE			(1<<10)		// Clock Chop Enable
#define	PSC_SPI_CFG_PSE			(1<<11)		// Port Swap Enable
#define	PSC_SPI_CFG_BI			(1<<12)		// Bit Clock Invert
#define	PSC_SPI_CFG_DIV			(0x3<<13)	// Clock Divider
#define	PSC_SPI_CFG_DIV_N(n)	((n&0x3)<<13)
#define	PSC_SPI_CFG_BRG			(0x3F<<15)	// Baud Rate Generator
#define	PSC_SPI_CFG_BRG_N(n)	((n&0x3F)<<15)
#define	PSC_SPI_CFG_DE			(1<<26)		//Device Enable
#define	PSC_SPI_CFG_DD			(1<<27)		// Diable DMA
#define	PSC_SPI_CFG_TRD			(0x3<<28)	// TX Request Depth
#define	PSC_SPI_CFG_TRD_N(n)	((n&0x3)<<28)
#define	PSC_SPI_CFG_RRD			(0x3<<30)	// Rx Request Depth
#define	PSC_SPI_CFG_RRD_N(n)	((n&0x3)<<30)

#define	PSC_SPI_MSK_MD			(1<<4)		// Master Done
#define	PSC_SPI_MSK_SD			(1<<5)		// Slave done
#define	PSC_SPI_MSK_TU			(1<<8)		// TX Fifo underflow
#define	PSC_SPI_MSK_TO			(1<<9)		// TX fifo overflow
#define	PSC_SPI_MSK_TR			(1<<10)		// TX Fifo request
#define	PSC_SPI_MSK_RU			(1<<11)		// RX Fifo underflow
#define	PSC_SPI_MSK_RO			(1<<12)		// RX fifo overflow
#define	PSC_SPI_MSK_RR			(1<<13)		// RX Fifo request
#define	PSC_SPI_MSK_MM			(1<<16)		// Multiple Master Error

#define PSC_SPI_PCR_MS			(1<<0)		// Master Start
#define PSC_SPI_PCR_TC			(1<<2)		// Tx Data Clear
#define PSC_SPI_PCR_SS			(1<<4)		// Slave Start
#define PSC_SPI_PCR_SP			(1<<5)		// Slave Stop
#define PSC_SPI_PCR_RC			(1<<6)		// Rx Data Clear

// Status Register is Read Only //
#define PSC_SPI_STS_SR			(1<<0)		// PSC Ready
#define PSC_SPI_STS_DR			(1<<1) 		// Device Ready	
#define PSC_SPI_STS_DI			(1<<2)		// Device INterrupt
#define PSC_SPI_STS_MB			(1<<4)		// Master BUsy
#define PSC_SPI_STS_SB			(1<<5)		// Slave Busy
#define PSC_SPI_STS_TR			(1<<8)		// Tx Rrequest
#define PSC_SPI_STS_TE			(1<<9)		// Tx Fifo Empty
#define PSC_SPI_STS_TF			(1<<10)		// Tx Fifo Full
#define PSC_SPI_STS_RR			(1<<11)		// Rx Rrequest
#define PSC_SPI_STS_RE			(1<<12)		// Rx Fifo Empty
#define PSC_SPI_STS_RF			(1<<13)		// Rx Fifo Full

#define	PSC_SPI_EVNT_MD			(1<<4)		// Master Done
#define	PSC_SPI_EVNT_SD			(1<<5)		// Slave done
#define	PSC_SPI_EVNT_TU			(1<<8)		// TX Fifo underflow
#define	PSC_SPI_EVNT_TO			(1<<9)		// TX fifo overflow
#define	PSC_SPI_EVNT_TR			(1<<10)		// TX Fifo request
#define	PSC_SPI_EVNT_RU			(1<<11)		// RX Fifo underflow
#define	PSC_SPI_EVNT_RO			(1<<12)		// RX fifo overflow
#define	PSC_SPI_EVNT_RR			(1<<13)		// RX Fifo request
#define	PSC_SPI_EVNT_MM			(1<<16)		// Multiple Master Error

#define PSC_SPI_TXRX_DATA		(0xFFFFFF<<0)	// Data
#define PSC_SPI_TXRX_DATA_N(n)	((n&0xFFFFFF)<<0)
#define PSC_SPI_TXRX_ST			(1<<28)		// Slave Select Toggle
#define PSC_SPI_TXRX_LC			(1<<29)		// Last Character -- Non-DMA only


/*
################################################################################################
#####                          I2S Register Definitions                                    #####
################################################################################################
*/

#define PSC_I2S_SEL			PSC_SEL
#define PSC_I2S_CTL			PSC_CTL
#define PSC_I2S_CFG			0x00000008
#define PSC_I2S_MSK			0x0000000C
#define PSC_I2S_PCR			0x00000010
#define PSC_I2S_STS			0x00000014
#define PSC_I2S_EVNT		0x00000018
#define PSC_I2S_TXRX		0x0000001C

#ifndef ASSEMBLER
typedef volatile struct 
{
	PSC_SELECT	psc;		//00,04
	uint32		cfg;		//08
	uint32		msk;		//0C
	uint32		pcr;		//10
	uint32		sts;		//14
	uint32		evnt;		//18
	uint32		txrx;		//1C
} PSC_I2S;
#endif

#define	PSC_I2S_CFG_MS			(1<<0)		// Master/Slafe
#define	PSC_I2S_CFG_MLF			(1<<1)		// MSB/LSB first
#define	PSC_I2S_CFG_LB			(1<<2)		// Loopback Mode
#define PSC_I2S_CFG_LEN			(0x1F<<4)	// Length mask
#define PSC_I2S_CFG_LEN_N(n)	((n&0x1F)<<4)	// Length 'n'
#define	PSC_I2S_CFG_XM			(1<<9)		// Transfer Mode
#define	PSC_I2S_CFG_MLJ			(1<<10)		// MSB/LSB Justified
#define	PSC_I2S_CFG_BUF			(1<<11)		// L/R Channel Buffer
#define	PSC_I2S_CFG_BI			(1<<12)		// Bit clock invert
#define PSC_I2S_CFG_BDIV  		(0x3<<13)	// Bit Clock Divider
#define PSC_I2S_CFG_BDIV_N(n)	((n&0x3)<<13)
#define	PSC_I2S_CFG_WI			(1<<15)		// Word Strobe Invert
#define	PSC_I2S_CFG_WS			(1<<16)		// Word Strobe
#define	PSC_I2S_CFG_WS_N(n)		((n&0xFF)<<16)
#define	PSC_I2S_CFG_DE			(1<<26)		// Device Enable
#define	PSC_I2S_CFG_TBS			(0x3<<28)	// TX Burst Size
#define	PSC_I2S_CFG_TBS_N(n)	((n&0x3)<<28)
#define	PSC_I2S_CFG_RBS			(0x3<<30)	// Rx Burst Size
#define	PSC_I2S_CFG_RBS_N(n)	((n&0x3)<<30)

#define	PSC_I2S_MSK_TD			(1<<4)		// Tx Done
#define	PSC_I2S_MSK_RD			(1<<5)		// Rx Done
#define	PSC_I2S_MSK_TU			(1<<8)		// TX Fifo underflow
#define	PSC_I2S_MSK_TO			(1<<9)		// TX fifo overflow
#define	PSC_I2S_MSK_TR			(1<<10)		// TX Fifo request
#define	PSC_I2S_MSK_RU			(1<<11)		// RX Fifo underflow
#define	PSC_I2S_MSK_RO			(1<<12)		// RX fifo overflow
#define	PSC_I2S_MSK_RR			(1<<13)		// RX Fifo request

#define PSC_I2S_PCR_TS			(1<<0)		// Tx start
#define PSC_I2S_PCR_TP			(1<<1)		// Tx Stop
#define PSC_I2S_PCR_TC			(1<<2)		// Tx Data Clear
#define PSC_I2S_PCR_RS			(1<<4)		// Rx Start
#define PSC_I2S_PCR_RP			(1<<5)		// Rx Stop
#define PSC_I2S_PCR_RC			(1<<6)		// Rx Data Clear

// Status Register is Read Only //
#define PSC_I2S_STS_SR			(1<<0)		// PSC Ready
#define PSC_I2S_STS_DR			(1<<1) 		// Device Ready	
#define PSC_I2S_STS_DI			(1<<2)		// Device INterrupt
#define PSC_I2S_STS_TB			(1<<4)		// Tx BUsy
#define PSC_I2S_STS_RB			(1<<5)		// Rx Busy
#define PSC_I2S_STS_TR			(1<<8)		// Tx Rrequest
#define PSC_I2S_STS_TE			(1<<9)		// Tx Fifo Empty
#define PSC_I2S_STS_TF			(1<<10)		// Tx Fifo Full
#define PSC_I2S_STS_RR			(1<<11)		// Rx Rrequest
#define PSC_I2S_STS_RE			(1<<12)		// Rx Fifo Empty
#define PSC_I2S_STS_RF			(1<<13)		// Rx Fifo Full

#define	PSC_I2S_EVNT_TD			(1<<4)		// Tx Done
#define	PSC_I2S_EVNT_RD			(1<<5)		// Rx Done
#define	PSC_I2S_EVNT_TU			(1<<8)		// TX Fifo underflow
#define	PSC_I2S_EVNT_TO			(1<<9)		// TX fifo overflow