encryption.h

嵌入式linux（arm9）的平台下

	uint32	key3_2;				//(0x0624)
	uint32	ihd_1;				//(0x0628)
	uint32	ihd_2;				//(0x062C)
	uint32	ihd_3;				//(0x0630)
	uint32	ihd_4;				//(0x0634)
	uint32	ihd_5;				//(0x0638)
	uint32	ohd_1;				//(0x063C)
	uint32	ohd_2;				//(0x0640)
	uint32	ohd_3;				//(0x0644)
	uint32	ohd_4;				//(0x0648)
	uint32	ohd_5;				//(0x064C)
	uint32	spi;				//(0x0650)
	uint32	seq_num;			//(0x0654)
	uint32	seq_num_mask1;		//(0x0658)
	uint32	seq_num_mask2;		//(0x065C)
	uint8	reserved1;			//(0x0660)
	uint32	sa_ptr_st_rec;		//(0x0664)
	uint8	reserved2;			//(0x0668)
	uint8	reserved3;			//(0x066C)
	uint8	reserved4;			//(0x0670)
	uint8	reserved5;			//(0x0674)
	uint32	mgmt0;				//(0x0678)
	uint32	mgmt1;				//(0x067C)

} PE_SA_REV0;
 #endif


#ifndef ASSEMBLER
typedef volatile struct
{
	uint32	cmd0;				//(0x0600)			// DATABOOT ERROR? USES 0X0000?
	uint32	cmd1;				//(0x0604)			// DATABOOK ERROR? USES 0X0004?
	uint8	reserved[0x8];		//(0x0608) 0C
	uint32	key1_1;				//(0x0610)
	uint32	key1_2;				//(0x0614)
	uint32	key2_1;				//(0x0618)
	uint32	key2_2;				//(0x061C)	
	uint8	reserved1[0x10];	//(0x0620) 24 28 2C
	uint32	arc4_ij;			//(0x0630)
	uint32	ptr_st_rec;			//(0x0634)
	uint8	reserved2[0x40];	//(0x0638)
	uint32	mgmt0;				//(0x0678)
	uint32	mgmt1;				//(0x067C)

} PE_SA_ARC4;
#endif



/************************************
*									*
* AU1550 ENCRYPTION BIT DEFINITIONS	*
*									*
************************************/


/*
SYSTEM INTERFACE REGISTERS
*/
#define PE_DIVIDER_CDIV			(3<<1)				// Clock divider for packet engine
#define PE_DIVIDER_CE			(1<<0)				// Clock enable for packet engine 
#define PE_HOSTINT_HINT			(1<<0)				// Host interrupt
#define PE_BUFFSTAT_STAT		(1<<0)				// Buffer status
#define PE_SBUSCFG_ADDR			(0xF<<4)			// Most significant nibble of system address
#define PE_SBUSCFG_C			(1<<1)				// Coherent (enable caching)
#define PE_SBUSCFG_PRI			(1<<0)				// Priority boost for system bus arbitration


/*
PACKET ENGINE GLOBAL REGISTERS
*/
#define PE_DMA_CFG_SUP			(1<<20)				// Suppress PDR ownership update
#define PE_DMA_CFG_EP			(1<<18)				// Apply endian swap for packet data
#define PE_DMA_CFG_ESA			(1<<17)				// Apply endian swap for SA data
#define PE_DMA_CFG_EPD			(1<<16)				// Apply endian swap for packet descriptors
#define PE_DMA_CFG_PFD			(1<<10)				// Packet follows descriptor
#define PE_DMA_CFG_SAP			(1<<9)				// SA precedes packet
#define PE_DMA_CFG_PE			(1<<8)				// Packet engine mode
#define PE_DMA_CFG_RP			(1<<1)				// Reset packet counter/pointers
#define PE_DMA_CFG_RPE			(1<<0)

#define PE_DMA_STAT_OUTSIZ		(0x3FF<<22)			// Output size
#define PE_DMA_STAT_INSIZ		(0x3FF<<12)			// Input size
#define PE_DMA_STAT_CA			(1<<9)				// Command queue active
#define PE_DMA_STAT_SPI			(1<<7)				// SPI mismatch
#define PE_DMA_STAT_ICV			(1<<6)				// ICV fault
#define PE_DMA_STAT_PF			(1<<5)				// Crypto pad fault
#define PE_DMA_STAT_OHD			(1<<4)				// Outer hash done
#define PE_DMA_STAT_IHD			(1<<3)				// Inner hash done
#define PE_DMA_STAT_ED			(1<<2)				// Encryption done
#define PE_DMA_STAT_OD			(1<<1)				// Output done
#define PE_DMA_STAT_ID			(1<<0)				// Input done

#define PE_PDR_BASE				(0xFFFFFFFF<<0)		// PDR base address
#define PE_RDR_BASE				(0xFFFFFFFF<<0)		// RDR base address

#define PE_RING_SIZE_OFFSET		(0xFFFF<<16)		// Descriptor ring offset
#define PE_RING_SIZE_SIZE	   	(0x1FF<<0)			// Descriptor ring size

#define PE_RING_POLL_C			(1<<31)				// Continuous
#define PE_RING_POLL_RETDIV		(0x3FF<<16)			// Ring retry divisor
#define PE_RING_POLL_POLLDIV	(0xFFF<<0)			// Ring poll divisor

#define PE_INT_RING_STAT_CQA	(1<<0)				// Command queue available

#define PE_EXT_RING_STAT		(0x3FF<<16)			// Index of next packet descriptor

#define PE_IO_THRESHOLD_OT		(0xF<<16)			// Output threshold
#define PE_IO_THRESHOLD_IT		(0xF<<0)			// Input threshold


/*
PACKET ENGINE DESCRIPTOR REGISTERS
*/
#define PE_CTRLSTAT_PCS			(0x1F<<27)			// Pad control/status
#define PE_CTRLSTAT_EC			(0xF<<20)			// Extended code
#define PE_CTRLSTAT_EE			(1<<19)				// Extended error
#define PE_CTRLSTAT_SN			(1<<18)				// Sequence number fail
#define PE_CTRLSTAT_PV			(1<<17)				// Pad verify fail
#define PE_CTRLSTAT_A			(1<<16)				// Authentication fail
#define PE_CTRLSTAT_NH			(0xFF<<8)			// Next header/pad value
#define PE_CTRLSTAT_HF			(1<<4)				// Hash final
#define PE_CTRLSTAT_NK			(1<<3)				// New key ARC4
#define PE_CTRLSTAT_LHD			(1<<2)				// Load SA hash digests
#define PE_CTRLSTAT_CD_HR  		(3<<0)				// Encryption core done and Host ready
#define PE_CTRLSTAT_HD			(1<0)
#define PE_CTRLSTAT_ED			(1<1)

#define PE_LENGTH_CD_HR			(3<<22)				// Encryption core done and host ready
#define PE_LENGTH_HD			(1<22)
#define PE_LENGTH_ED			(1<23)

#define PE_LENGTH_LENGTH		(0xFFFFF<<0)		// Length


/*
SA RECORD FORMAT
*/

#define PE_SA_CMD0_SH			(1<<29)				// Save hash state
#define PE_SA_CMD0_SIV			(1<<28)				// Save IV
#define PE_SA_CMD0_LH			(0x3<<26)			// Load hash state
#define PE_SA_CMD0_LIV			(0x3<<24)			// Load IV
#define PE_SA_CMD0_HP			(1<<19)				// Header processing
#define PE_SA_CMD0_HA			(0xF<<12)			// Hash algorithm
#define PE_SA_CMD0_CA			(0xF<<8)			// Crypto algorithm
#define PE_SA_CMD0_CP			(0x3<<6)			// Crypto pad
#define PE_SA_CMD0_OPG			(0x3<<4)			// Operation group
#define PE_SA_CMD0_IO			(1<<3)				// Inbound/Outbound
#define PE_SA_CMD0_OPC			(0x7<<0)			// Operation code

#define PE_SA_CMD1_SS			(1<<30)				// Save ARC4 state
#define PE_SA_CMD1_AS			(1<<29)				// ARC4 stateless/stateful
#define PE_SA_CMD1_KLEN			(0x1F<<24)			// ARC4 key length
#define PE_SA_CMD1_CHOFF		(0xFF<<16)			// Hash / encrypt offset
#define PE_SA_CMD1_SA			(1<<15)				// SA revision
#define PE_SA_CMD1_HM			(1<<12)				// HMAC control
#define PE_SA_CMD1_CM			(3<<1)				// Cryptographic mode
#define PE_SA_CMD1_MB			(1<<5)				// Mutable bit handling
#define PE_SA_CMD1_IP			(1<<4)				// IPv4 / IPv6
#define PE_SA_CMD1_PAD			(1<<3)				// Copy inbound pad to output
#define PE_SA_CMD1_PAY  		(1<<2)				// Copy payload to output
#define PE_SA_CMD1_HD   		(1<<1)				// Copy header to output



/*
DMA REGISTERS
*/


#define PE_DMA_STAT_MTA			(1<<19)				// Master transfer active
#define PE_DMA_STAT_TLEN		(0xFFF<<0)			// Transfew length

#define PE_DMA_BURST_MAX_TSIZE	(0x3FF<<2)			// Maximum transfer size

#define PE_ENDIAN_SBL3			(3<<22)				// Byte lane sources for byte 3
#define PE_ENDIAN_SBL2			(3<<20)				// Byte lane sources for byte 2
#define PE_ENDIAN_SBL1			(3<<18)				// Byte lane sources for byte 1
#define PE_ENDIAN_SBL0			(3<<16)				// Byte lane sources for byte 0
#define PE_ENDIAN_MBL3			(3<<6)				// Byte lane sources for byte 3
#define PE_ENDIAN_MBL2			(3<<4)				// Byte lane sources for byte 2
#define PE_ENDIAN_MBL1  		(3<<2)				// Byte lane sources for byte 1
#define PE_ENDIAN_MBL0			(3<<0)				// Byte lane sources for byte 0

/*
RANDOM NUMBER GENERATOR REGISTERS
*/

#define PE_RNG_STAT_B			(1<<0)				// Busy

#define PE_RNG_TEST_CNTL_RL		(1<<10)				// Reset LFSRs
#define PE_RNG_TEST_CNTL_TL		(1<<9)				// Test LFSRs
#define PE_RNG_TEST_CNTL_TA		(1<<8)				// Test alarm
#define PE_RNG_TEST_CNTL_SC		(1<<7)				// Short cycle
#define PE_RNG_TEST_CNTL_TC		(1<<6)				// Test counter
#define PE_RNG_TEST_CNTL_DA		(1<<5)				// Disable alarm
#define PE_RNG_TEST_CNTL_TR2	(1<<4)				// Test ring1
#define PE_RNG_TEST_CNTL_TR1	(1<<3)				// Test ring2
#define PE_RNG_TEST_CNTL_T		(1<<2)				// Test run
#define PE_RNG_TEST_CNTL_TM		(1<<1)				// Test mode
#define PE_RNG_TEST_CNTL_TO		(1<<0)				// Test ring output

#define PE_RNG_ENTA_ENTA		(0xFFFF<<0)			// Entropy A
#define PE_RNG_ENTB_ENTB		(0xFFFF<<0)			// Entropy B

#define PE_RNG_CFG_RCOUNT		(0x3F<<0)			// Reset count
#define PE_RNG_CFG_R2D		    (0x3<<3)			// Ring2 delay
#define PE_RNG_CFG_R1D  		(0x3<<0)			// Ring1 delay
#define PE_RNG_CFG_LFSR1_0 		(0xFFFFFFFF<<0)		// Bits [31:0] of 49-bit LFSR1
#define PE_RNG_CFG_LFSR1_1 		(0x1FFFF<<0)		// Bits [48:32] of 49-bit LFSR1
													// DATABOOK ERROR? NOT CONSISTENT WITH LFSR2

#define PE_RNG_CFG_LFSR2_0 		(0xFFFFFFFF<<0)		// Bits [31:0] of 48-bit LFSR2
#define PE_RNG_CFG_LFSR2_1 		(0x1FFFF<<0)		// Bits [47:32] of 48-bit LFSR2
													// DATABOOK ERROR? NOT CONSISTENT WITH LFSR1

/*
INTERRUPT CONTROL REGISTERS
*/
#define PE_INT_HU_STAT_CD		(1<<9)				// Packet engine context done
#define PE_INT_HU_STAT_ER		(1<<4)				// Packet engine error
#define PE_INT_HU_STAT_DD		(1<<3)				// Packet engine descriptor done
#define PE_INT_HU_STAT_QD		(1<<1)				// Command queue done

#define PE_INT_HM_STAT_CD		(1<<9)				// Packet engine context done
#define PE_INT_HM_STAT_ER		(1<<4)				// Packet engine error
#define PE_INT_HM_STAT_DD		(1<<3)				// Packet engine descriptor done
#define PE_INT_HM_STAT_QD		(1<<1)				// Command queue done

#define PE_INT_HI_CLR_CD		(1<<9)				// Packet engine context done
#define PE_INT_HI_CLR_ER		(1<<4)				// Packet engine error
#define PE_INT_HI_CLR_DD		(1<<3)				// Packet engine descriptor done
#define PE_INT_HI_CLR_QD		(1<<1)				// Command queue done

#define PE_INT_HI_MASK_CD		(1<<9)				// Packet engine context done
#define PE_INT_HI_MASK_ER		(1<<4)				// Packet engine error
#define PE_INT_HI_MASK_DD		(1<<3)				// Packet engine descriptor done
#define PE_INT_HI_MASK_QD		(1<<1)				// Command queue done

#define PE_INT_HI_CFG_PSC		(1<<1)				// Pulse self-clear
#define PE_INT_HI_CFG_TYP		(1<<0)				// Interrupt host output type


/*
DEVICE ID AND CONTROL REGISTERS
*/

#define PE_CRYPTO_CNTL_RNE		(1<<17)				// RNG enable
#define PE_CRYPTO_CNTL_3DE		(1<<17)				// 3-DES enable

#define PE_DEV_ID_VENID			(0xFFFF<<16)		// Vendor ID
#define PE_DEV_ID_DEVID			(0xFFFF<<0)			// Device ID

#define PE_DEV_INFO_SFC			(0xFFFF<<8)			// Supported function code
#define PE_DEV_INFO_REV			(0xFFFF<<0)			// Revision

#ifndef ASSEMBLER
typedef volatile struct
{
	PE_CONFIG 	cfg;			//0x0000 - 0x0088	
	uint8		res0[20];		//0x008c - 0x0090
    PE_INT_CNTL intctl;			//0x00A0 - 0x00B8
	uint8		res1[8];		//0x00BC - 0x00C0
	PE_DMA		dma;			//0x00C4 - 0x00E0
	uint8		res2[28];		//0x00E4 - 0x00FC
	PE_RNG		rng;			//0x0100 - 0x0138
	/* There are some context registers that are not defined in this sturcture */
	/* The space is included so the mapping to virtual address will cover entire block */	
	uint8		context[1388];	//0x013C - 0x06A4

} AU1550_CRYPTO;
#endif
		 					
#endif