encryption.h

嵌入式linux（arm9）的平台下

// AU1550
// Block: ENCRYPTION CORE
// Base Address: 0x14008000

#ifndef _AU1550_ENCRYPTION_H__
#define _AU1550_ENCRYPTION_H__
#define ASSEMBLER_CTG
#define PE_PHYS_ADDRESS		(0x14008000)

/*****************************************
*										 *
* AU1550 ENCRYPTION REGISTER DEFINITIONS *
*										 *
******************************************/

/*
PACKET ENGINE AND SYSTEM INTERFACE REGISTERS
*/
#define PE_CTRLSTAT			(0x0000)
#define PE_SOURCE			(0x0004)
#define PE_DEST				(0x0008)
#define PE_SA				(0x000C)
#define PE_LENGTH			(0x0010)

#define PE_DIVIDER			(0x0020)
#define PE_HOSTINT			(0x0024)
#define PE_BUFFSTAT			(0x0028)
#define PE_SBUSCFG			(0x002C)

#define PE_GLBDMACFG   	(0x0040)
#define PE_GLBDMASTAT  	(0x0044)
#define PE_GLBPDRBASE  	(0x0048)
#define PE_GLBRDRBASE  	(0x004C)
#define PE_GLBRSIZE		(0x0050)
#define PE_GLBRPOLL		(0x0054)
#define PE_GLBQSTAT		(0x0058)
#define PE_GLBEXTRSTAT	(0x005C)
#define PE_GLBTHRESH	(0x0060)

#define PE_GLBRAMTEST	(0x0074)				// DATABOOK ERROR? NOT DEFINED ANYWHERE?

#ifndef ASSEMBLER
typedef volatile struct
{
	uint32	ctrlstat;			//(0x0000)
	uint32	source;				//(0x0004)
	uint32 	dest;				//(0x0008)
	uint32 	sa;					//(0x000C)
	uint32 	length;				//(0x0010)
	uint8	reserved[0x0C];		//(0x0014) 18 1C
	uint32 	divider;			//(0x0020)
	uint32 	hostint;			//(0x0024)
	uint32 	buffstat;			//(0x0028)
	uint32 	sbuscfg;			//(0x002C)
	uint8	reserved1[0x10];	//(0x0030) 34 38 3C
	uint32 	glbdmacfg;			//(0x0040)
	uint32 	glbdmastat;			//(0x0044)
	uint32 	glbpdrbase;			//(0x0048)
	uint32 	glbrdrbase;			//(0x004C)
	uint32 	glbrsize;			//(0x0050)
	uint32 	glbrpoll;			//(0x0054)
	uint32 	glbqstat;			//(0x0058)
	uint32 	glbextrstat;		//(0x005C)
	uint32 	glbthresh;			//(0x0060)
	uint8	reserved2[0x10];	//(0x0064) 68 6C 70
	uint32	glbramtest;			//(0x0074) // DATABOOK ERROR? NOT DEFINED ANYWHERE?
	uint8	reserved3[0x08];	//(0x0078) 7C
	uint32	devctrl;			//(0x0080)
	uint32	devid;				//(0x0084)
	uint32	devinfo;			//(0x0088)
} PE_CONFIG;
#endif

/*
DEVICE ID AND CONTROL REGISTERS
*/
#define PE_CRYPTO_CNTL		(0x0080)
#define PE_DEV_ID			(0x0084)
#define PE_DEV_INFO			(0x0088)


/*
INTERRUPT CONTROL REGISTERS
*/
#define PE_INT_HU_STAT		(0x00A0)
#define PE_INT_HM_STAT		(0x00A4) // 2 #defines at same address...
#define PE_INT_HI_CLR		(0x00A4) // Will this work? Or change to PE_INT_HM_STAT_HI_CLR?
#define PE_INT_HI_MASK		(0x00A8)
#define PE_INT_HI_CFG		(0x00AC)
#define PE_INT_HI_RD_DESC	(0x00B4)
#define PE_INT_HI_DESC_CNT	(0x00B8)

#ifndef ASSEMBLER
typedef volatile struct
{
	uint32	hu_stat;		//(0x00A0)
	union {
		uint32	hm_stat;   	//(0x00A4)
		uint32	hi_clr;	   	//(0x00A4)
	} u;
	uint32	hi_mask;		//(0x00A8)
	uint32	hi_cfg;			//(0x00AC)
	uint8	reserved;			//(0x00B0)
	uint32	hi_rd_desc;		//(0x00B4)
	uint32	hi_desc_cnt;	//(0x00B8)
} PE_INT_CNTL;
#endif

/*
DMA CONTROLLER REGISTERS
*/
#define PE_DMA_SOURCE		(0x00C4)
#define PE_DMA_DEST			(0x00C8)
#define PE_DMA_STAT			(0x00CC)

#define PE_DMA_BURST		(0x00D4)
#define PE_ENDIAN			(0x00E0)

#ifndef ASSEMBLER
typedef volatile struct
{
	uint32	source;			//(0x00C4)
	uint32	dest;			//(0x00C8)
	uint32	stat;			//(0x00CC)
	uint8	reserved;			//(0x00D0)
	uint32	burst;			//(0x00D4)
	uint8	reserved1[0x08];	//(0x00D8) DC
	uint32	endian;				//(0x00E0)
} PE_DMA;
#endif
/*
RNG REGISTERS
*/
#define PE_RNG_OUT			(0x0100)
#define PE_RNG_STAT			(0x0104)
#define PE_RNG_TEST_CNTL	(0x0108)
#define PE_RNG_ENTA			(0x010C)
#define PE_RNG_ENTB			(0x0110)
#define PE_RNG_SEED0		(0x0114)
#define PE_RNG_SEED1		(0x0118)
#define PE_RNG_SEED2		(0x011C)
#define PE_RNG_COUNT		(0x0120)
#define PE_RNG_ALARM		(0x0124)
#define PE_RNG_CFG			(0x0128)
#define PE_RNG_LFSR1_0		(0x012C)
#define PE_RNG_LFSR1_1		(0x0130)
#define PE_RNG_LFSR2_0		(0x0134)
#define PE_RNG_LFSR2_1		(0x0138)

#ifndef ASSEMBLER
typedef volatile struct
{
	uint32	out;			//(0x0100)
	uint32	stat;			//(0x0104)
	uint32	test_cntl;		//(0x0108)
	uint32	enta;			//(0x010C)
	uint32	entb;			//(0x0110)
	uint32	seed0;			//(0x0114)
	uint32	seed1;			//(0x0118)
	uint32	seed2;			//(0x011C)
	uint32	count;			//(0x0120)
	uint32	alarm;			//(0x0124)
	uint32	cfg;			//(0x0128)
	uint32	lfsr1_0;		//(0x012C)
	uint32	lfsr1_1;		//(0x0130)
	uint32	lfsr2_0;		//(0x0134)
	uint32	lfsr2_1;		//(0x0138)
} PE_RNG;
#endif
/*
SA RECORD FORMAT
*/
#define PE_SA_CMD0			(0x0600)			// DATABOOT ERROR? USES 0X0000?
#define PE_SA_CMD1			(0x0604)			// DATABOOK ERROR? USES 0X0004?

#define PE_SA_KEY1_1		(0x0610)
#define PE_SA_KEY1_2		(0x0614)
#define PE_SA_KEY2_1		(0x0618)
#define PE_SA_KEY2_2		(0x061C)
#define PE_SA_KEY3_1		(0x0620)
#define PE_SA_KEY3_2		(0x0624)
#define PE_SA_KEY4_1		(0x0628)
#define PE_SA_KEY4_2		(0x062C)
#define PE_SA_IHD_1			(0x0630)
#define PE_SA_IHD_2			(0x0634)
#define PE_SA_IHD_3			(0x0638)
#define PE_SA_IHD_4			(0x063C)
#define PE_SA_IHD_5			(0x0640)
#define PE_SA_OHD_1			(0x0644)
#define PE_SA_OHD_2			(0x0648)
#define PE_SA_OHD_3			(0x064C)
#define PE_SA_OHD_4			(0x0650)
#define PE_SA_OHD_5			(0x0654)

#define PE_SA_IV_1			(0x066C)
#define PE_SA_IV_2			(0x0670)
#define PE_SA_IV_3			(0x0674)
#define PE_SA_IV_4			(0x0678)
#define PE_SA_HASH_BYTE_CNT	(0x067C)
#define PE_SA_IHD_1_MIR		(0x0680)
#define PE_SA_IHD_2_MIR		(0x0684)
#define PE_SA_IHD_3_MIR		(0x0688)
#define PE_SA_IHD_4_MIR		(0x068C)
#define PE_SA_IHD_5_MIR		(0x0690)
#define PE_SA_ICV_1			(0x0694)
#define PE_SA_ICV_2			(0x0698)
#define PE_SA_ICV_3			(0x069C)

#define PE_SA_DATA_IN_FIFO	(0x06A0)
#define PE_SA_DATA_OUT_FIFO	(0x06A4)


#ifndef ASSEMBLER
typedef volatile struct
{
	uint32	iv_1;			//not sure
	uint32	iv_2;			//not sure
	uint32	iv_3;			//not sure
	uint32	iv_4;			//not sure
	uint32	hash_byte_cnt;	//not sure
	uint32	ihd_1_mir;		//not sure
	uint32	ihd_2_mir;		//not sure
	uint32	ihd_3_mir;		//not sure
	uint32	ihd_4_mir;		//not sure
	uint32	ihd_5_mir;		//not sure
} STATE_RECORD;
#endif

#ifndef ASSEMBLER
typedef volatile struct
{
	uint32	cmd0;				//(0x0600)			// DATABOOT ERROR? USES 0X0000?
	uint32	cmd1;				//(0x0604)			// DATABOOK ERROR? USES 0X0004?
	uint8	reserved[0x8];		//(0x0608) 0C
	uint32	key1_1;				//(0x0610)
	uint32	key1_2;				//(0x0614)
	uint32	key2_1;				//(0x0618)
	uint32	key2_2;				//(0x061C)
	uint32	key3_1;				//(0x0620)
	uint32	key3_2;				//(0x0624)
	uint32	key4_1;				//(0x0628)
	uint32	key4_2;				//(0x062C)
	uint32	ihd_1;				//(0x0630)
	uint32	ihd_2;				//(0x0634)
	uint32	ihd_3;				//(0x0638)
	uint32	ihd_4;				//(0x063C)
	uint32	ihd_5;				//(0x0640)
	uint32	ohd_1;				//(0x0644)
	uint32	ohd_2;				//(0x0648)
	uint32	ohd_3;				//(0x064C)
	uint32	ohd_4;				//(0x0650)
	uint32	ohd_5;				//(0x0654)
	uint32	spi;				//(0x0658)
	uint32	seq_num;			//(0x065C)
	uint32	seq_num_mask1;		//(0x0660)
	uint32	seq_num_mask2;		//(0x0664)
	uint8	reserved1;			//(0x0668)
	uint32	ptr_st_rec;			//(0x066C)
	uint8	reserved2;			//(0x0670)
	uint8	reserved3;			//(0x0674)
	uint32	mgmt0;				//(0x0678)
	uint32	mgmt1;				//(0x067C)
} PE_SA_REV1;
#endif

	
#ifndef ASSEMBLER
typedef volatile struct
{
	uint32	cmd0;				//(0x0600)			// DATABOOT ERROR? USES 0X0000?
	uint32	cmd1;				//(0x0604)			// DATABOOK ERROR? USES 0X0004?
	uint8	reserved[0x8];		//(0x0608) 0C
	uint32	key1_1;				//(0x0610)
	uint32	key1_2;				//(0x0614)
	uint32	key2_1;				//(0x0618)
	uint32	key2_2;				//(0x061C)
	uint32	key3_1;				//(0x0620)