📄 smc.h
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/********************************************************************* * * Copyright: * Advanced Micro Devices, AMD. All Rights Reserved. * You are hereby granted a copyright license to use, modify, and * distribute the SOFTWARE so long as this entire notice is * retained without alteration in any modified and/or redistributed * versions, and that such modified versions are clearly identified * as such. No licenses are granted by implication, estoppel or * otherwise under any patents or trademarks of AMD. This * software is provided on an "AS IS" basis and without warranty. * * To the maximum extent permitted by applicable law, AMD * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY * ACCOMPANYING WRITTEN MATERIALS. * * To the maximum extent permitted by applicable law, IN NO EVENT * SHALL AMD BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. * * AMD assumes no responsibility for the maintenance and support * of this software. ********************************************************************* * * File: smc.h * * Purpose: Definitions for Au1550 PSC * * $RCSfile: SMC.h,v $ * $Author: cgray $ * $Revision: 1.2 $ * $Date: 2003/11/10 21:28:56 $ ************************************************************************/#ifndef __SMC_1550_TEST_H#define __SMC_1550_TEST_H// Statis Bus Register Configuration Offsets#define SMC_DTY (0x0) #define SMC_RO (0x3)#define SMC_PM (0x4)#define SMC_BS (0x5)#define SMC_H (0x6) #define SMC_EW (0x7)#define SMC_TS (0x8)#define SMC_BE (0x9)#define SMC_AV (0xA)#define SMC_BV (0xC)#define SMC_DIV (0xD)#define SMC_TA (0x10)#define SMC_BEB (0x11)#define SMC_DE (0x13)#define SMC_S (0x14)#define SMC_AS (0x15)#define SMC_NW (0x16)// SMC Device Type#define SMC_RAM (0x0 << DTY)#define SMC_I0 (0x1 << DTY)#define SMC_PCMCIA (0x2 << DTY)#define SMC_NOR (0x3 << DTY)#define SMC_NAND (0x5 << DTY)//Static Bus Register Timing Offset#define SMC_TA (0x0)#define SMC_TPM (0x6)#define SMC_TCSW (0xA)#define SMC_TWP (0xE)#define SMC_TCSOFF (0x14)#define SMC_T0 (0x17)#define SMC_TCSH (0x18)#define SMC_TWCS (0x1C)#define SMC_T1 (0x1F)// PCMCIA Bus Register Timing Offset#define PCMCIA_TISU (0x0)#define PCMCIA_TIST (0x5)#define PCMCIA_TMIH (0xB)#define PCMCIA_TMSU (0x11)#define PCMCIA_TMST (0x18)// PCMCIA Bus Register Configuration Offsets#define PCMCIA_CSMASK (0x0)#define PCMCIA_CSBA (0xE)#define PCMCIA_EN (0x1C) // SMC Register Configuration Bit Set#define SMC_READ_ONLY (0x1 << SMC_RO)#define SMC_PAGE_MODE (0x1 << SMC_PM)#define SMC_BURST_SIZE(n) ((n&0x1) << SMC_BS)#define SMC_HALF_BUS (1 << SMC_H)#define SMC_TIME_SCALE(n) ((n&0x1) << SMC_TS)#define SMC_LITTLE_ENDIAN (1 << SMC_BE)#define SMC_BURST_VISIBLE (1 << SMC_BV)#define SMC_RCLK_DIV(n) ((n&0x7) << SMC_DIV)#define SMC_TCSH_RW (1 << SMC_TA)#define SMC_PHV(n) ((n&0x3) << SMC_BEB)#define SMC_SYNC_MODE (1 << SMC_S)#define SMC_ADD_B4_CS (1 << SMC_AS)#define SMC_NAND_WIDTH(n) ((n&0x1) << SMC_NW)// SMC Register Timing Bit Set#define SMC_BUS_LENGTH(n) ((n&0x3F) << SMC_TA)#define SMC_BURST_LEN(n) ((n&0xF) << SMC_TPM)#define SMC_CS_2WR(n) ((n&0xF) << SMC_TCSW)#define SMC_WR_LEN(n) ((n&0x3F) << SMC_TWP)#define SMC_ADDR_HOLD_OE(T1,T0) (T1 << SMC_T1 | T0 << SMC_T0)#define SMC_CS_HOLD(n) ((n&0xF) << SMC_TCSH)#define SMC_CS_HOLD_WR(n) ((n&0x3) << SMC_TWCS)//PCMCIA Register Timing Bit Set#define PCMCIA_CSETUP_IO(n) ((n&0x1F) << PCMCIA_TISU)#define PCMCIA_CSLEN(n) ((n&0x3F) << PCMCIA_TIST)#define PCMCIA_HOLDTIME(n) ((n&0x3F) << PCMCIA_TMIH)#define PCMCIA_CSETUP_MEM(n) ((n&0x7F) << PCMCIA_TMSU)#define PCMCIA_PWE_WIDTH(n) ((n&0xFF) << PCMCIA_TMST)//PCMCIA Register Configuration Bit Set#define PCMCIA_CS_ADDR_MASK(n) ((n&0x3FFF) << PCMCIA_CSMASK)#define PCMCIA_CS_BASE_ADDR(n) ((n&0x3FFF) << PCMCIA_CSBA)#define PCMCIA_EN (1 << PCMCIA_EN)// NAND Flash Control Registers Offsets.// NAND BASE Registers location is the CSX base address#define MEM_STNAND (0x1100)#define MEM_STNAND_CMD (0x0)#define MEM_STNAND_ADDR (0x4)#define MEM_STNAND_DATA (0x20) // Global SMC Declarations#define SMC_PHYS_ADDRESS (0x14000000)#define SMC_MEMSTCFG0 (0x1000)#define SMC_MEMSTCFG1 (0x1010)#define SMC_MEMSTCFG2 (0x1020)#define SMC_MEMSTCFG3 (0x1030)#define SMC_MEMSTTIME0 (0x1004)#define SMC_MEMSTTIME1 (0x1014)#define SMC_MEMSTTIME2 (0x1024)#define SMC_MEMSTTIME3 (0x1034)#define SMC_STADDR0 (0x1008)#define SMC_STADDR1 (0x1018)#define SMC_STADDR2 (0x1028)#define SMC_STADDR3 (0x1038)// Status Register for SMC Block#define MEM_STSTAT (0x1004)// Status Register Bit Offsets#define BSY (0x0)#define BOOT (0x1)#define EWT (0x4)#define PWT (0x5) #endif /* __SMC_1550_TEST_H */⌨️ 快捷键说明
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