sdram.h

嵌入式linux（arm9）的平台下

#define	SD_STRIDE_TD_POS    	(24)
#define	SD_STRIDE_TD_MASK   	(0xFF)
#define	SD_STRIDE_TD(val)      	((val&&SD_STRIDE_TD_MASK)<<SD_STRIDE_TD_POS)
#define SD_STRIDE_TD_GET(val)	((val>>SD_STRIDE_TD_POS)&&SD_STRIDE_TD_MASK)


//=========================================================
//	Bit definitions for SDRAM Mode Write & Exteded Mode Write Command Register, Offset = 0x0080, 0x88, 0x90
//===========================================
// OFFSET	: 13;	// Values for Address pins A12:A0
//-----------------------------------
#define SD_WRITE_EXTERN_OFFSET_POS    	(0)
#define	SD_WRITE_EXTERN_OFFSET_MASK   	(0x1FF)
#define	SD_WRITE_EXTERN_OFFSET(val)     ((val&&SD_WRITE_EXTERN_OFFSET_MASK)<<SD_WRITE_EXTERN_OFFSET_POS)
#define SD_WRITE_EXTERN_OFFSET_GET(val)	((val>>SD_WRITE_EXTERN_OFFSET_POS)&&SD_WRITE_EXTERN_OFFSET_MASK)

//-----------------------------------
// BA0	: 1;	// Value for sdram BA0 pin
//-----------------------------------
#define SD_WRITE_EXTERN_BA0_POS    	(30)
#define	SD_WRITE_EXTERN_BA0_MASK   	(0x1)
#define	SD_WRITE_EXTERN_BA0_BIT 	(1<<SD_WRITE_EXTERN_BA0_POS)
#define	SD_WRITE_EXTERN_BA0(val)    ((val&&SD_WRITE_EXTERN_BA0_MASK)<<SD_WRITE_EXTERN_BA0_POS)
#define SD_WRITE_EXTERN_BA0_GET(val)	((val>>SD_WRITE_EXTERN_BA0_POS)&&SD_WRITE_EXTERN_BA0_MASK)

//-----------------------------------
// BA1	: 1;	// Value for sdram BA0 pin
//-----------------------------------
#define SD_WRITE_EXTERN_BA1_POS    	(31)
#define	SD_WRITE_EXTERN_BA1_MASK   	(0x1)
#define	SD_WRITE_EXTERN_BA1_BIT 	(1<<SD_WRITE_EXTERN_BA1_POS)
#define	SD_WRITE_EXTERN_BA1(val)    ((val&&SD_WRITE_EXTERN_BA1_MASK)<<SD_WRITE_EXTERN_BA1_POS)
#define SD_WRITE_EXTERN_BA1_GET(val)	((val>>SD_WRITE_EXTERN_BA1_POS)&&SD_WRITE_EXTERN_BA1_MASK)


//=========================================================
//	SyncFlash Mode Write & Exteded Mode Write Command Register, Offset = 0x0098, 0xA0, 0xA8 
//    mem_sdmode_cs[MT] must be set for SyncFlash Mode Write CS command to occur.
//===========================================
// OFFSET	: 13;	// Values for Address pins A12:A0
//-----------------------------------
#define SD_LOAD_EXT_CMD_OFFSET_POS    	(0)
#define	SD_LOAD_EXT_CMD_OFFSET_MASK   	(0x1FF)
#define	SD_LOAD_EXT_CMD_OFFSET(val)     ((val&&SD_LOAD_EXT_CMD_OFFSET_MASK)<<SD_LOAD_EXT_CMD_OFFSET_POS)
#define SD_LOAD_EXT_CMD_OFFSET_GET(val)	((val>>SD_LOAD_EXT_CMD_OFFSET_POS)&&SD_LOAD_EXT_CMD_OFFSET_MASK)

//-----------------------------------
// BA0	: 1;	// Value for sdram BA0 pin
//-----------------------------------
#define SD_LOAD_EXT_CMD_BA0_POS    	(30)
#define	SD_LOAD_EXT_CMD_BA0_MASK   	(0x1)
#define	SD_LOAD_EXT_CMD_BA0_BIT 	(1<<SD_LOAD_EXT_CMD_BA0_POS)
#define	SD_LOAD_EXT_CMD_BA0(val)     ((val&&SD_LOAD_EXT_CMD_BA0_MASK)<<SD_LOAD_EXT_CMD_BA0_POS)
#define SD_LOAD_EXT_CMD_BA0_GET(val)	((val>>SD_LOAD_EXT_CMD_BA0_POS)&&SD_LOAD_EXT_CMD_BA0_MASK)

//-----------------------------------
// BA1	: 1;	// Value for sdram BA0 pin
//-----------------------------------
#define SD_LOAD_EXT_CMD_BA1_POS    	(31)
#define	SD_LOAD_EXT_CMD_BA1_MASK   	(0x1)
#define	SD_LOAD_EXT_CMD_BA1_BIT 	(1<<SD_LOAD_EXT_CMD_BA1_POS)
#define	SD_LOAD_EXT_CMD_BA1(val)     ((val&&SD_LOAD_EXT_CMD_BA1_MASK)<<SD_LOAD_EXT_CMD_BA1_POS)
#define SD_LOAD_EXT_CMD_BA1_GET(val)	((val>>SD_LOAD_EXT_CMD_BA1_POS)&&SD_LOAD_EXT_CMD_BA1_MASK)

//-----------------------------------
#define SD_LOAD_EXT_CMD_MODE(val)    	(0 + ((val&&SD_LOAD_EXT_CMD_OFFSET_MASK)<<SD_LOAD_EXT_CMD_OFFSET_POS))
#define SD_LOAD_EXT_CMD_EXTMODE(val)    (SD_LOAD_EXT_CMD_BA0_BIT + ((val&&SD_LOAD_EXT_CMD_OFFSET_MASK)<<SD_LOAD_EXT_CMD_OFFSET_POS))


//======================================================================
//  Au1550 SDRAM Controller Register Structure and Bit Field Definitions
//
//  Au1550 SDRAM Controller Registers were DESIGNED as 64-bit Entries.
//   Therefore, a 64-bit data item must be built.
//=====================================

#ifdef __AU1550

#if 1 	// 1 = use last working defs
typedef	volatile struct { uint32 low32, high32;} SDRAM_REG;
#define	AU1550MEM_PAD	int	au1550	:32;
#else	// Test long long  vs. dword or struct
typedef	volatile long long SDRAM_REG;
#define	AU1550MEM_PAD	
#endif

#else
typedef	volatile uint32 SDRAM_REG;
#define	AU1550MEM_PAD	
#endif


#ifndef ASSEMBLER
//===========================================
//	Bit definitions for Chip Select Timing Configuration Registers, Offset = 0x0000-0x0018
//===========================================
typedef volatile union 
{
uint64 cs_ctrl;
//uint32 cs_ctrl;
struct {
  int	tcas	: 3;	//	Minimum CAS latency timing
  int	RSVD3	: 1;
  int	trcd_rd	: 3;	//	RAS to CAS delay for Reads, value = 1 less than required # mem bus Clock cycles
  int	RSVD7	: 1;
  int	trcd_wr	: 3;	//	RAS to CAS delay for Writes, value = 1 less than required # mem bus Clock cycles
  int	RSVD11	: 1;
  int	trp 	: 2;	//	RAS Precharge Time, value = 1 less than required # mem bus Clock cycles
  int	twtr	: 2;	//	Write to Read Turnaround Time, value = 1 less than required # mem bus Clock cycles
  int	tras	: 4;	//	Minimum Time for a complete access, value = 1 less than min. # Clock cycles
  int	twr 	: 3;	//	Write to Precharge Time, value = 1 less than min. # Clock cycles
  int	RSVD22	: 1;	
  int	skew	: 2;	//	(DDR Only) SKEW between external CAS latency and Internal Tcas
  int	mt  	: 2;	//	Memory Type (0=SDR, 1=DDR, 2=rsvd, 3=SyncFlash)
  int	ec  	: 2;	//	ErrorCode (Reserved)
  int	bw  	: 2;	//	External Bus Width (0=32-bit, 1=16-bit, 2=rsvd, 3=rsvd)
  AU1550MEM_PAD	
	};
} SDRAM_CS_MODE_REG;



//=========================================================
//	Bit definitions for Chip Select Address Configuration Registers, Offset = 0x0020-0x0038
//===========================================
typedef volatile union
{
uint32	mctrl;
struct {
  int	csmask	: 10;	// CSBA Mask Bits: IF ((PhysAddr & csmask)== csba) Activate CS#
  int	csba	: 10;	// ChipSelect Base Address bits 31:22
  int	e   	: 1;	// E bit non-zero to enable the Chip Select (DFLT = 0)
  int	    	: 3;
  int	cs  	: 3;	//	Column Address Size in bits (DFLT = 1 for 8-bits)
  int	    	: 1;
  int	rs  	: 2;	//	Row Address Size in bits (DFLT = 0 for 11-bits)
  int	f   	: 1;	//	F bit set = no caching master execpt the core will access this space (DFLT = 0)
  int	bs  	: 1;	//	Select # of Banks (DFLT = 0 for 2-banks)
  AU1550MEM_PAD	
	};
} SDRAM_CS_ADDR_REG;


//=========================================================
//	Bit definitions for Global Configuration Register 'A', Offset = 0x0040
//===========================================
typedef volatile union
{
uint32	sdconfiga;
struct {
  int	ref_int	: 18;	// Max. distributer refresh internal in system bus clocks
  int		: 2;	// Reserved
  int	ce0	: 1;	// Ce0 Clock Enable for Clock Pad 0
  int	ce1	: 1;	// Ce1 Clock Enable for Clock Pad 1
  int		: 2;	// Reserved
  int	rpt	: 2;	// # Refresh cycles performed for each Refresh Period
  int		: 1;	// Reserved
  int	e	: 1;	// Enable Refresh
  int	trc	: 4;	// Min. time from start of Auto-Refresh cycle to an activate cmd for all CS
  AU1550MEM_PAD	
	};
} SDRAM_CONFIG_A_REG;


//=========================================================
//	Bit definitions for Global Configuration Register 'B', Offset = 0x0048
//===========================================
typedef volatile union
{
uint32	sdconfigb;
struct {
  int	txsr: 5;	// Number of NOP commands required on exit from self-refresh mode scalled by 16 (0 = 16)
  int		: 2;	// Reserved
  int	ba	: 1;	// Block Access: 1 = memory controller blocks all transactions for [(TSRX+1)*16] clocks
  int		: 7;	// Reserved
  int	cr	: 1;	// Clock Ratio: 0 = divide SBUS by 2 for SDRAM BUS, 1 = No divide
  int		: 1;	// Reserved
  int	ds	: 1;	// Pad Select - Setting to 1 Enables Increased Drive Strength 
  int	lso	: 1;	// Level Shifter Override: 1 = level shifters in the output path to always on
  int	cb	: 1;	// Comparatr Bypass: 1 = enable input data path to bypass the DVREF comparator
  int		: 4;	// Reserved
  int	psel: 2;	// Address Pin Select to use for Auto-Precharge: 0= AD10, 1=AD8, 2&3=Reserved
  int	pm	: 1;	// Power Mode Enable: = 1 negates DCKE to memory when chip select is idle.
  int	hp	: 1;	// Half-power mode enable: = 1, disables internal bus transactions for ((TXSR+1)*16) clocks
  int	eib	: 1;	// Enable Interrupt on Boundary Errors for Stride Mode
  int		: 3;	// Reserved
  AU1550MEM_PAD	
	};
} SDRAM_CONFIG_B_REG;


//=========================================================
//	Bit definitions for STATUS Register, Offset = 0x0050
//===========================================
typedef volatile union
{
uint32	sdstat;
struct {
  int	bound	: 4;	// Bound Error: BOUND[3:2] = Initial ChipSelect, BOUND[1:0] = Stride Config Reg.
  int		: 20;	// Reserved
  int	slf	: 1;	// Bit set when memories are in Self-Refresh-Mode: 1 = DCKE is disabled 
  int	lpm	: 1;	// Low Power Mode: bit reflects the state of the memory DCKE bit.
  int		: 2;	// Reserved
  int	be	: 1;	// Boundary Error occurred during Stride Operation.
  int		: 3;	// Reserved
  AU1550MEM_PAD	
	};
} SDRAM_STAT_REG;


//=========================================================
//	Bit definitions for STRIDE Feature Configuration, Offset = 0x0060-0x0070
//===========================================
typedef volatile union
{
uint32	sdstride;
struct {
  int	offset	: 11;	// Number of BYTEs to skip for next burst
  int	    	: 1;	// Reserved
  int	count	: 3;	// # consecutive 8-bit accesses before adding Offset
  int	    	: 5;	// Reserved
  int	tm  	: 4;	// For Internal Testing SDSTRIDE0 Only: Control DLL duty cycle
  int	td  	: 8;	// For Internal Testing SDSTRIDE0 Only: W/R DLL duty cycle
  AU1550MEM_PAD	
	};
} SDRAM_STRIDE_REG;


//=========================================================
//	Bit definitions for SDRAM Mode Write & Exteded Mode Write Command Register, Offset = 0x0080, 0x88, 0x90
//===========================================
typedef volatile union
{		// SDRAM Mode Write & Exteded Mode Write Command Register
uint32	sdextmode;
struct {
  int	offset	: 13;	// Values for Address pins A12:A0
  int	    	: 16;	// Reserved
  int	ba0 	: 1;	// Value for BA0 pin
  int	ba1 	: 1;	// Value for BA1 pin
  AU1550MEM_PAD	
	};
} SDRAM_EXT_MODE_REG;

//===========================================
//
//===========================================
typedef volatile union
{		// mem_sdmode_cs[MT] must be set for SyncFlash Mode Write CS command to occur.
uint32	sdsfextmode;
struct {
  int	offset	: 13;	// Values for Address pins A12:A0
  int	    	: 16;	// Reserved
  int	ba0 	: 1;	// Value for BA0 pin
  int	ba1 	: 1;	// Value for BA1 pin
  AU1550MEM_PAD	
	};
} SDRAM_SF_CMD_REG;

//=========================================================
//  Au1550 SDRAM Controller Register Structure
//
//===========================================
typedef volatile struct
{
SDRAM_CS_MODE_REG sdmode_cs0;	// Chip Select 0 Timing & Function	0x0000
SDRAM_CS_MODE_REG sdmode_cs1;	// Chip Select 1 Timing & Function	0x0008
SDRAM_CS_MODE_REG sdmode_cs2;	// Chip Select 2 Timing & Function	0x0010
SDRAM_REG reserved_18;	// Reserved             	0x0018

SDRAM_CS_ADDR_REG sdaddr_cs0;	// Chip Select 0 Base Addr & Size	0x0020
SDRAM_CS_ADDR_REG sdaddr_cs1;	// Chip Select 1 Base Addr & Size	0x0028
SDRAM_CS_ADDR_REG sdaddr_cs2;	// Chip Select 2 Base Addr & Size	0x0030
SDRAM_REG reserved_38;	// Reserved             	0x0018

SDRAM_CONFIG_A_REG sdconfig_a; 	// Global Configuration Register A	0x0040
SDRAM_CONFIG_B_REG sdconfig_b; 	// Global Configuration Register B	0x0048
SDRAM_STAT_REG sdstat;       	// Read Only Block Status Information	0x0050
SDRAM_REG sderraddr;         	// OFFending ADDress of last Error	0x0058
SDRAM_STRIDE_REG sdstride0;  	// STRIDE0 Configuration Reg.       0x0060
SDRAM_STRIDE_REG sdstride1;  	// STRIDE1 Configuration Reg.   	0x0068
SDRAM_STRIDE_REG sdstride2;  	// STRIDE2 Configuration Reg.   	0x0070
SDRAM_REG reserved_78;	// Reserved             	0x0078

SDRAM_EXT_MODE_REG sdwrxcs0;	// Write data to CS0 Mode Regs	0x0080
SDRAM_EXT_MODE_REG sdwrxcs1;	// Write data to CS1 Mode Regs	0x0088
SDRAM_EXT_MODE_REG sdwrxcs2;	// Write data to CS2 Mode Regs	0x0090
SDRAM_REG reserved_98;	// Reserved                  	0x0098

SDRAM_SF_CMD_REG sdldxcmdcs0;	// Write data to CS0 SFlash cmd Reg	0x00A0
SDRAM_SF_CMD_REG sdldxcmdcs1;	// Write data to CS1 SFlash cmd Reg	0x00A8
SDRAM_SF_CMD_REG sdldxcmdcs2;	// Write data to CS2 SFlash cmd Reg	0x00B0
SDRAM_REG reserved_B8;	// Reserved                  	0x00B8

SDRAM_REG sdprecharge_cmd;	// Issue PRECHARGE to all enabled Chip Selects	0x00C0
SDRAM_REG sdauto_refresh_cmd;// Issue REFRESH to all enabled Chip Selects	0x00C8
SDRAM_REG sdself_refresh;	// Writes Toggle the SELF_REFRESH mode. 	0x00D0
SDRAM_REG reserved_D8;	// Reserved                  	0x00D8
} MEM_CTRL_REGS;
#endif		// ASSEMBLER

#endif