sdram.h

嵌入式linux（arm9）的平台下

};

//-----------------------------------
//	Row Address Size in bits (DFLT = 0)
//-----------------------------------
#define	SD_CSADDR_RS_POS	(28)
#define	SD_CSADDR_RS_MASK	(0x3)
#define	SD_CSADDR_RS(val)  	((val&&SD_CSADDR_RS_MASK)<<SD_CSADDR_RS_POS)
#define SD_CSADDR_RS_GET(val)	((val>>SD_CSADDR_RS_POS)&&SD_CSADDR_RS_MASK)

enum SD_ROWS {
	RS_11=0,	// Row Addr is 11 bits (Default)
	RS_12,  	// Row Addr is 12 bits
	RS_13,  	// Row Addr is 13 bits
	RS_14   	// Row Addr is 14 bits
};

//-----------------------------------
//	F bit set = no caching master execpt the core will access this space (DFLT = 0)
//-----------------------------------
#define	SD_CSADDR_F_POS	(30)
#define	SD_CSADDR_F_MASK	(0x1)
#define	SD_CSADDR_F_BIT 	(1<<SD_CSADDR_F_POS)
#define	SD_CSADDR_F(val) 	((val&&SD_CSADDR_F_MASK)<<SD_CSADDR_F_POS)
#define SD_CSADDR_F_GET(val) 	((val>>SD_CSADDR_F_POS)&&SD_CSADDR_F_MASK)

//-----------------------------------
//	Select # of Banks (DFLT = 0)
//-----------------------------------
#define	SD_CSADDR_BS_POS	(31)
#define	SD_CSADDR_BS_MASK	(0x1)
#define	SD_CSADDR_BS_BIT	(1<<SD_CSADDR_BS_POS)
#define	SD_CSADDR_BS(val)	((val&&SD_CSADDR_BS_MASK)<<SD_CSADDR_BS_POS)
#define SD_CSADDR_BS_GET(val) ((val>>SD_CSADDR_BS_POS)&&SD_CSADDR_BS_MASK)

enum SD_BANKS {
	BS_2=0, 	// 0 = 2 bank device
	BS_4,   	// 1 = 4 bank device
};


//=========================================================
//	Bit definitions for Global Configuration Register 'A', Offset = 0x0040
//===========================================
// REF_INT : 18;	// Max. distributer refresh internal in system bus clocks
//-----------------------------------
#define	SD_GCR_A_REF_INT_POS	(0)
#define	SD_GCR_A_REF_INT_MASK	(0x3FFFF)
#define	SD_GCR_A_REF_INT(val)	((val&&SD_GCR_A_REF_INT_MASK)<<SD_GCR_A_REF_INT_POS)
#define	SD_GCR_A_REF_INT_GET(val)	((val>>SD_GCR_A_REF_INT_POS)&&SD_GCR_A_REF_INT_MASK)

//-----------------------------------
// CE0	: 1;	// Ce0 Clock Enable for Clock Pad 0
//-----------------------------------
#define	SD_GCR_A_CE0_POS	(20)
#define	SD_GCR_A_CE0_MASK	(0x1)
#define	SD_STATUS_CE0_BIT	(1<<SD_STATUS_CE0_POS)
#define	SD_GCR_A_CE0(val)	((val&&SD_GCR_A_CE0_MASK)<<SD_GCR_A_CE0_POS)
#define	SD_GCR_A_CE0_GET(val)	((val>>SD_GCR_A_CE0_POS)&&SD_GCR_A_CE0_MASK)

//-----------------------------------
// CE1	: 1;	// Ce1 Clock Enable for Clock Pad 1
//-----------------------------------
#define	SD_GCR_A_CE1_POS	(21)
#define	SD_GCR_A_CE1_MASK	(0x1)
#define	SD_STATUS_CE1_BIT	(1<<SD_STATUS_CE1_POS)
#define	SD_GCR_A_CE1(val)	((val&&SD_GCR_A_CE1_MASK)<<SD_GCR_A_CE1_POS)
#define	SD_GCR_A_CE1_GET(val)	((val>>SD_GCR_A_CE1_POS)&&SD_GCR_A_CE1_MASK)

//-----------------------------------
// RPT	: 2;	// # Refresh cycles performed for each Refresh Period
//-----------------------------------
#define	SD_GCR_A_RPT_POS	(24)
#define	SD_GCR_A_RPT_MASK	(0x3)
#define	SD_GCR_A_RPT(val)	((val&&SD_GCR_A_RPT_MASK)<<SD_GCR_A_RPT_POS)
#define	SD_GCR_A_RPT_GET(val)	((val>>SD_GCR_A_RPT_POS)&&SD_GCR_A_RPT_MASK)

//-----------------------------------
// E	: 1;	// Enable Refresh
//-----------------------------------
#define	SD_GCR_A_E_POS  	(27)
#define	SD_GCR_A_E_MASK 	(0x1)
#define	SD_STATUS_E_BIT 	(1<<SD_STATUS_E_POS)
#define	SD_GCR_A_E(val) 	((val&&SD_GCR_A_E_MASK)<<SD_GCR_A_E_POS)
#define	SD_GCR_A_E_GET(val)	((val>>SD_GCR_A_E_POS)&&SD_GCR_A_E_MASK)

//-----------------------------------
// Trc	: 4;	// Min. time from start of Auto-Refresh cycle to an activate cmd for all CS
//-----------------------------------
#define	SD_GCR_A_TRC_POS	(28)
#define	SD_GCR_A_TRC_MASK	(0xF)
#define	SD_GCR_A_TRC(val)	((val&&SD_GCR_A_TRC_MASK)<<SD_GCR_A_TRC_POS)
#define	SD_GCR_A_TRC_GET(val)	((val>>SD_GCR_A_TRC_POS)&&SD_GCR_A_TRC_MASK)


//=========================================================
//	Bit definitions for Global Configuration Register 'B', Offset = 0x0048
//===========================================
// Txsr	: 5;	// Number of NOP commands required on exit from self-refresh mode scalled by 16 (0 = 16)
//-----------------------------------
#define	SD_GCR_B_TXSR_POS	(0)
#define	SD_GCR_B_TXSR_MASK	(0x1F)
#define	SD_GCR_B_TXSR(val)	((val&&SD_GCR_B_TXSR_MASK)<<SD_GCR_B_TXSR_POS)
#define	SD_GCR_B_TXSR_GET(val)	((val>>SD_GCR_B_TXSR_POS)&&SD_GCR_B_TXSR_MASK)

//-----------------------------------
// BA	: 1;	// Block Access: 1 = memory controller blocks all transactions for [(TSRX+1)*16] clocks
//-----------------------------------
#define	SD_GCR_B_BA_POS	(7)
#define	SD_GCR_B_BA_MASK	(0x1)
#define	SD_STATUS_BA_BIT	(1<<SD_STATUS_BA_POS)
#define	SD_GCR_B_BA(val)	((val&&SD_GCR_B_BA_MASK)<<SD_GCR_B_BA_POS)
#define	SD_GCR_B_BA_GET(val)	((val>>SD_GCR_B_BA_POS)&&SD_GCR_B_BA_MASK)

//-----------------------------------
// CR	: 1;	// Clock Ratio: 0 = divide SBUS by 2 for SDRAM BUS, 1 = No divide
//-----------------------------------
#define	SD_GCR_B_CR_POS 	(15)
#define	SD_GCR_B_CR_MASK	(0x1)
#define	SD_STATUS_CR_BIT	(1<<SD_STATUS_CR_POS)
#define	SD_GCR_B_CR(val)	((val&&SD_GCR_B_CR_MASK)<<SD_GCR_B_CR_POS)
#define	SD_GCR_B_CR_GET(val)	((val>>SD_GCR_B_CR_POS)&&SD_GCR_B_CR_MASK)

//-----------------------------------
// PS	: 1;	// Drive Strength - Setting to 1 Enables Increased Drive Strength 
//-----------------------------------
#define	SD_GCR_B_DS_POS 	(17)
#define	SD_GCR_B_DS_MASK	(0x1)
#define	SD_STATUS_DS_BIT	(1<<SD_STATUS_DS_POS)
#define	SD_GCR_B_PS(val)	((val&&SD_GCR_B_DS_MASK)<<SD_GCR_B_DS_POS)
#define	SD_GCR_B_DS_GET(val)	((val>>SD_GCR_B_DS_POS)&&SD_GCR_B_DS_MASK)

//-----------------------------------
// LSO	: 1;	// Level Shifter Override: 1 = level shifters in the output path to always on
//-----------------------------------
#define	SD_GCR_B_LSO_POS	(18)
#define	SD_GCR_B_LSO_MASK	(0x1)
#define	SD_STATUS_LSO_BIT	(1<<SD_STATUS_LSO_POS)
#define	SD_GCR_B_LSO(val)	((val&&SD_GCR_B_LSO_MASK)<<SD_GCR_B_LSO_POS)
#define	SD_GCR_B_LSO_GET(val)	((val>>SD_GCR_B_LSO_POS)&&SD_GCR_B_LSO_MASK)

//-----------------------------------
// CB	: 1;	// Comparatr Bypass: 1 = enable input data path to bypass the DVREF comparator
//-----------------------------------
#define	SD_GCR_B_CB_POS  	(19)
#define	SD_GCR_B_CB_MASK 	(0x1)
#define	SD_STATUS_CB_BIT	(1<<SD_STATUS_CB_POS)
#define	SD_GCR_B_CB(val) 	((val&&SD_GCR_B_CB_MASK)<<SD_GCR_B_CB_POS)
#define	SD_GCR_B_CB_GET(val)	((val>>SD_GCR_B_CB_POS)&&SD_GCR_B_CB_MASK)

//-----------------------------------
//PSEL	: 2;	// Address Pin Select to use for Auto-Precharge: 0= AD10, 1=AD8, 2&3=Reserved
//-----------------------------------
#define	SD_GCR_B_PSEL_POS	(24)
#define	SD_GCR_B_PSEL_MASK	(0x3)
#define	SD_GCR_B_PSEL(val)	((val&&SD_GCR_B_PSEL_MASK)<<SD_GCR_B_PSEL_POS)
#define	SD_GCR_B_PSEL_GET(val)	((val>>SD_GCR_B_PSEL_POS)&&SD_GCR_B_PSEL_MASK)

//-----------------------------------
// PM	: 1;	// Power Mode Enable: = 1 negates DCKE to memory when chip select is idle.
//-----------------------------------
#define	SD_GCR_B_PM_POS 	(26)
#define	SD_GCR_B_PM_MASK	(0x1)
#define	SD_STATUS_PM_BIT	(1<<SD_STATUS_PM_POS)
#define	SD_GCR_B_PM(val)	((val&&SD_GCR_B_PM_MASK)<<SD_GCR_B_PM_POS)
#define	SD_GCR_B_PM_GET(val)	((val>>SD_GCR_B_PM_POS)&&SD_GCR_B_PM_MASK)

//-----------------------------------
// HP	: 1;	// Half-power mode enable: = 1, disables internal bus transactions for ((TXSR+1)*16) clocks
//-----------------------------------
#define	SD_GCR_B_HP_POS 	(27)
#define	SD_GCR_B_HP_MASK	(0x1)
#define	SD_STATUS_HP_BIT	(1<<SD_STATUS_HP_POS)
#define	SD_GCR_B_HP(val)	((val&&SD_GCR_B_HP_MASK)<<SD_GCR_B_HP_POS)
#define	SD_GCR_B_HP_GET(val)	((val>>SD_GCR_B_HP_POS)&&SD_GCR_B_HP_MASK)

//-----------------------------------
// EIB	: 1;	// Enable Interrupt on Boundary Errors for Stride Mode
//-----------------------------------
#define	SD_GCR_B_EIB_POS 	(28)
#define	SD_GCR_B_EIB_MASK	(0x1)
#define	SD_STATUS_EIB_BIT	(1<<SD_STATUS_EIB_POS)
#define	SD_GCR_B_EIB(val)	((val&&SD_GCR_B_EIB_MASK)<<SD_GCR_B_EIB_POS)
#define	SD_GCR_B_EIB_GET(val)	((val>>SD_GCR_B_EIB_POS)&&SD_GCR_B_EIB_MASK)


//=========================================================
//	Bit definitions for STATUS Register, Offset = 0x0050
//===========================================
// BOUND	: 1;	// Boundary Error: [3:2]= Initial Chip Select, [1:0]= Stride Configuration Register
//-----------------------------------
#define	SD_STATUS_BOUND_POS 	(0)
#define	SD_STATUS_BOUND_MASK	(0xF)
#define	SD_STATUS_BOUND(val)   	((val&&SD_STATUS_BOUND_MASK)<<SD_STATUS_BOUND_POS)
#define SD_STATUS_BOUND_GET(val)	((val>>SD_STATUS_BOUND_POS)&&SD_STATUS_BOUND_MASK)

//-----------------------------------
// SLF	: 1;	// Set when memories are in SLF mode, also, DCKE is disabled
//-----------------------------------
#define	SD_STATUS_SLF_POS	(24)
#define	SD_STATUS_SLF_MASK	(0x1)
#define	SD_STATUS_SLF_BIT	(1<<SD_STATUS_SLF_POS)
#define	SD_STATUS_SLF(val)   	((val&&SD_STATUS_SLF_MASK)<<SD_STATUS_SLF_POS)
#define SD_STATUS_SLF_GET(val)	((val>>SD_STATUS_SLF_POS)&&SD_STATUS_SLF_MASK)

//-----------------------------------
// LPM	: 1;	// Reflect the state of the memory DCKE bit.
//-----------------------------------
#define	SD_STATUS_LPM_POS	(25)
#define	SD_STATUS_LPM_MASK	(0x1)
#define	SD_STATUS_LPM_BIT	(1<<SD_STATUS_LPM_POS)
#define	SD_STATUS_LPM(val)   	((val&&SD_STATUS_LPM_MASK)<<SD_STATUS_LPM_POS)
#define SD_STATUS_LPM_GET(val)	((val>>SD_STATUS_LPM_POS)&&SD_STATUS_LPM_MASK)

//-----------------------------------
// BE	: 1;	// Boundary Error ccurred during STRIDE Operation, ref. SD_GCR_B[EIB]
//-----------------------------------
#define	SD_STATUS_BE_POS	(28)
#define	SD_STATUS_BE_MASK	(0x1)
#define	SD_STATUS_BE_BIT	(1<<SD_STATUS_BE_POS)
#define	SD_STATUS_BE(val)   	((val&&SD_STATUS_BE_MASK)<<SD_STATUS_BE_POS)
#define SD_STATUS_BE_GET(val)	((val>>SD_STATUS_BE_POS)&&SD_STATUS_BE_MASK)


//=========================================================
//	Bit definitions for STRIDE Feature Configuration, Offset = 0x0060-0x0070
//===========================================
//	Byte Offset to be added to initial address when Count-Accesses has occurred.
//-----------------------------------
#define	SD_STRIDE_OFFSET_POS	(0)
#define	SD_STRIDE_OFFSET_MASK	(0x3FF)
#define	SD_STRIDE_OFFSET(val)   	((val&&SD_STRIDE_OFFSET_MASK)<<SD_STRIDE_OFFSET_POS)
#define SD_STRIDE_OFFSET_GET(val)	((val>>SD_STRIDE_OFFSET_POS)&&SD_STRIDE_OFFSET_MASK)

//-----------------------------------
//	Number of consecutive 8-bit data values to return before adding Offset.
//-----------------------------------
#define	SD_STRIDE_COUNT_POS 	(12)
#define	SD_STRIDE_COUNT_MASK	(0x7)
#define	SD_STRIDE_COUNT(val)    	((val&&SD_STRIDE_COUNT_MASK)<<SD_STRIDE_COUNT_POS)
#define SD_STRIDE_COUNT_GET(val)	((val>>SD_STRIDE_COUNT_POS)&&SD_STRIDE_COUNT_MASK)

//-----------------------------------
//   SD_STRIDE_COUNT field definitions....
//-----------------------------------
enum SD_STRIDE_COUNT {
	STRIDE_BURST_SIZE_4=2,	// 2 = 4 Byte Burst
	STRIDE_BURST_SIZE_8, 	// 3 = 8 Byte Burst
	STRIDE_BURST_SIZE_16 	// 4 = 16 Byte Burst
};

//-----------------------------------
//	DLL Timing Mode control register  (STRIDE_0 Only, For testing)
//-----------------------------------
#define	SD_STRIDE_TM_POS	(20)
#define	SD_STRIDE_TM_MASK	(0xF)
#define	SD_STRIDE_TM(val)  	((val&&SD_STRIDE_TM_MASK)<<SD_STRIDE_TM_POS)
#define SD_STRIDE_TM_GET(val)	((val>>SD_STRIDE_TM_POS)&&SD_STRIDE_TM_MASK)

//-----------------------------------
//   TM field definitions....
// TM = 0xxx  Normal Mode, Closed Loop system
//-----------------
#define	SD_TM_NM_CL_MSK     	(1<<3)
#define	SD_TM_NM_CL_ENA     	(0<<3)

//-----------------
// TM = 100x  Normal Mode, Closed Loop system, Duty Cycle Reg Updates as in Normal Mode.
//-----------------
#define	SD_TM_NM_CL_DCRU_MSK	(7<<1)
#define	SD_TM_NM_CL_DCRU_ENA	(0x8)

//-----------------
// TM = 1010  Open Loop system, Duty Cycle Reg is Static
//-----------------
#define	SD_TM_OL_DCR_S_MSK  	(0xF)
#define	SD_TM_OL_DCR_S_ENA  	(0xA)

//-----------------
// TM = 1011  Open Loop system, Duty Cycle Reg Updates 1 time TM[0] is one-shot & req 4-clks after setting
//-----------------
#define	SD_TM_OL_DCU_1_MSK  	(0xF)
#define	SD_TM_OL_DCU_1_ENA  	(OxB)

//-----------------
// TM = 11xx  Load DLL Duty Cycle Reg with TD field.
//-----------------
#define	SD_TM_LDDCR_MSK     	(3<<2)
#define	SD_TM_LDDCR_ENA     	(3<<2)
//
enum STRIDE_TM {
	TM_NM_CL=0,     	// 0xxx = Normal Mode, Closed Loop system
	TM_NM_CL_DCRU=0x8, 	// 100x = Normal Mode, Closed Loop system, Duty Cycle Reg Updates as in Normal Mode.
	TM_OL_DCR_S=0XA,   	// 1010 = Open Loop system, Duty Cycle Reg is Static
	TM_OL_DCU_1=0xB, 	// 1011  Open Loop system, Duty Cycle Reg Updates 1 time TM[0] is one-shot & req 4-clks after setting
	TM_LDDCR=0xC    	// 11xx  Load DLL Duty Cycle Reg with TD field.
};


//-----------------------------------
//	Timing value loaded to DLL Duty Cycle Register (STRIDE_0 Only, For testing)
//-----------------------------------