📄 ddma.h
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#define DDMA_DESCSRC_STRIDE2DIM_SAM (28)#define DDMA_DESCSRC_STRIDE2DIM_SAM_N(n) ((n&3)<<DDMA_DESCSRC_STRIDE2DIM_SAM) #define DDMA_DESCSRC_STRIDE2DIM_SAM_INC DDMA_DESCSRC_STRIDE2DIM_SAM_N(0) #define DDMA_DESCSRC_STRIDE2DIM_SAM_DEC DDMA_DESCSRC_STRIDE2DIM_SAM_N(1) #define DDMA_DESCSRC_STRIDE2DIM_SAM_STATIC DDMA_DESCSRC_STRIDE2DIM_SAM_N(2) #define DDMA_DESCSRC_STRIDE2DIM_SAM_BURST DDMA_DESCSRC_STRIDE2DIM_SAM_N(3)#define DDMA_DESCSRC_STRIDE2DIM_STS (30)#define DDMA_DESCSRC_STRIDE2DIM_STS_N(n) ((n&3)<<DDMA_DESCSRC_STRIDE2DIM_STS) #define DDMA_DESCSRC_STRIDE2DIM_STS_1 DDMA_DESCSRC_STRIDE2DIM_STS_N(0) #define DDMA_DESCSRC_STRIDE2DIM_STS_2 DDMA_DESCSRC_STRIDE2DIM_STS_N(1) #define DDMA_DESCSRC_STRIDE2DIM_STS_4 DDMA_DESCSRC_STRIDE2DIM_STS_N(2) #define DDMA_DESCSRC_STRIDE2DIM_STS_8 DDMA_DESCSRC_STRIDE2DIM_STS_N(3)/* * Bit definitions for dest stride/block 1 dimensional */#define DDMA_DESCDST_STRIDE_DS (0)#define DDMA_DESCDST_STRIDE_DS_N(n) ((n&0x3fff)<<DDMA_DESCDST_STRIDE_DS)#define DDMA_DESCDST_STRIDE_DB (14)#define DDMA_DESCDST_STRIDE_DB_N(n) ((n&0x3Fff)<<DDMA_DESCDST_STRIDE_DB)#define DDMA_DESCDST_STRIDE_DAM (28)#define DDMA_DESCDST_STRIDE_DAM_N(n) ((n&3)<<DDMA_DESCDST_STRIDE_DAM) #define DDMA_DESCDST_STRIDE_DAM_INC DDMA_DESCDST_STRIDE_DAM_N(0) #define DDMA_DESCDST_STRIDE_DAM_DEC DDMA_DESCDST_STRIDE_DAM_N(1) #define DDMA_DESCDST_STRIDE_DAM_STATIC DDMA_DESCDST_STRIDE_DAM_N(2) #define DDMA_DESCDST_STRIDE_DAM_BURST DDMA_DESCDST_STRIDE_DAM_N(3)#define DDMA_DESCDST_STRIDE_DTS (30)#define DDMA_DESCDST_STRIDE_DTS_N(n) ((n&3)<<DDMA_DESCDST_STRIDE_DTS) #define DDMA_DESCDST_STRIDE_DTS_1 DDMA_DESCDST_STRIDE_DTS_N(0) #define DDMA_DESCDST_STRIDE_DTS_2 DDMA_DESCDST_STRIDE_DTS_N(1) #define DDMA_DESCDST_STRIDE_DTS_4 DDMA_DESCDST_STRIDE_DTS_N(2) #define DDMA_DESCDST_STRIDE_DTS_8 DDMA_DESCDST_STRIDE_DTS_N(3)/* * Bit definitions for dest stride/block 2 dimensional */#define DDMA_DESCDST_STRIDE2DIM_DC (0)#define DDMA_DESCDST_STRIDE2DIM_DC_N(n) ((n&0x3ff)<<DDMA_DESCDST_STRIDE2DIM_DC)#define DDMA_DESCDST_STRIDE2DIM_DS (11)#define DDMA_DESCDST_STRIDE2DIM_DS_N(n) ((n&0x1ff)<<DDMA_DESCDST_STRIDE2DIM_DS)#define DDMA_DESCDST_STRIDE2DIM_DB (21)#define DDMA_DESCDST_STRIDE2DIM_DB_N(n) ((n&0x7f)<<DDMA_DESCDST_STRIDE2DIM_DB)#define DDMA_DESCDST_STRIDE2DIM_DAM (28)#define DDMA_DESCDST_STRIDE2DIM_DAM_N(n) ((n&3)<<DDMA_DESCDST_STRIDE2DIM_DAM) #define DDMA_DESCDST_STRIDE2DIM_DAM_INC DDMA_DESCDST_STRIDE2DIM_DAM_N(0) #define DDMA_DESCDST_STRIDE2DIM_DAM_DEC DDMA_DESCDST_STRIDE2DIM_DAM_N(1) #define DDMA_DESCDST_STRIDE2DIM_DAM_STATIC DDMA_DESCDST_STRIDE2DIM_DAM_N(2) #define DDMA_DESCDST_STRIDE2DIM_DAM_BURST DDMA_DESCDST_STRIDE2DIM_DAM_N(3)#define DDMA_DESCDST_STRIDE2DIM_DTS (30)#define DDMA_DESCDST_STRIDE2DIM_DTS_N(n) ((n&3)<<DDMA_DESCDST_STRIDE2DIM_DTS) #define DDMA_DESCDST_STRIDE2DIM_DTS_1 DDMA_DESCDST_STRIDE2DIM_DTS_N(0) #define DDMA_DESCDST_STRIDE2DIM_DTS_2 DDMA_DESCDST_STRIDE2DIM_DTS_N(1) #define DDMA_DESCDST_STRIDE2DIM_DTS_4 DDMA_DESCDST_STRIDE2DIM_DTS_N(2) #define DDMA_DESCDST_STRIDE2DIM_DTS_8 DDMA_DESCDST_STRIDE2DIM_DTS_N(3)/* * Bit definitions for descriptor "next" pointer */#define DDMA_DESCNEXTPTR_NPTR (0)#define DDMA_DESCNEXTPTR_NPTR_N(n) ((n&0x1ffffff)<<DDMA_DESCNEXTPTR_NPTR)#define DDMA_DESCNEXTPTR_MS (1<<27)#define DDMA_DESCNEXTPTR_BBC (28)#define DDMA_DESCNEXTPTR_BBC_N(n) ((n&3)<<28)#ifndef ASSEMBLERtypedef volatile struct{ DDMA_CHANNEL channel[DDMA_NUM_CHANNELS]; // Start at offset 1400 2000 -- 1400 2f00 uint32 config; // 0x1400 3000 uint32 intstatus; // 0x1400 3004 uint32 throttle; // 0x1400 3008 uint32 intenable; // 0x1400 300c} DDMA;#endif/* * Bit definitions for General Configuration */#define DDMA_CONFIG_AL (1<<0)#define DDMA_CONFIG_AH (1<<1)#define DDMA_CONFIG_AF (1<<2)#define DDMA_CONFIG_C64 (1<<8)/* * Bit definitions for Interrupt Status */#define DDMA_INTSTAT_CHAN0 (1<<0)#define DDMA_INTSTAT_CHAN1 (1<<1)#define DDMA_INTSTAT_CHAN2 (1<<2)#define DDMA_INTSTAT_CHAN3 (1<<3)#define DDMA_INTSTAT_CHAN4 (1<<4)#define DDMA_INTSTAT_CHAN5 (1<<5)#define DDMA_INTSTAT_CHAN6 (1<<6)#define DDMA_INTSTAT_CHAN7 (1<<7)#define DDMA_INTSTAT_CHAN8 (1<<8)#define DDMA_INTSTAT_CHAN9 (1<<9)#define DDMA_INTSTAT_CHAN10 (1<<10)#define DDMA_INTSTAT_CHAN11 (1<<11)#define DDMA_INTSTAT_CHAN12 (1<<12)#define DDMA_INTSTAT_CHAN13 (1<<13)#define DDMA_INTSTAT_CHAN14 (1<<14)#define DDMA_INTSTAT_CHAN15 (1<<15)/* * DDMA Peripheral Addresses */#define DDMA_UART0_TX_ID (0)#define DDMA_UART0_RX_ID (1)#define DDMA_UART3_TX_ID (2)#define DDMA_UART3_RX_ID (3)#define DDMA_REQ0_ID (4)#define DDMA_GPIO4_ID DDMA_REQ0_ID#define DDMA_REQ1_ID (5)#define DDMA_GPIO5_ID DDMA_REQ1_ID#define DDMA_REQ2_ID (6)#define DDMA_GPIO208_ID DDMA_REQ2_ID#define DDMA_REQ3_ID (7)#define DDMA_GPIO209_ID DDMA_REQ3_ID#define DDMA_USB_DEVICE_ENDPOINT_0_RX_ID (8)#define DDMA_USB_DEVICE_ENDPOINT_0_TX_ID (9)#define DDMA_USB_DEVICE_ENDPOINT_1_TX_ID (10)#define DDMA_USB_DEVICE_ENDPOINT_2_TX_ID (11)#define DDMA_USB_DEVICE_ENDPOINT_3_RX_ID (12)#define DDMA_USB_DEVICE_ENDPOINT_4_RX_ID (13)#define DDMA_PSC0_TX_ID (14)#define DDMA_PSC0_RX_ID (15)#define DDMA_PSC1_TX_ID (16)#define DDMA_PSC1_RX_ID (17)#define DDMA_PSC2_TX_ID (18)#define DDMA_PSC2_RX_ID (19)#define DDMA_PSC3_TX_ID (20)#define DDMA_PSC3_RX_ID (21)#define DDMA_PCI_WRITE_ID (22)#define DDMA_NAND_FLASH_ID (23)#define DDMA_ETHERNET_MAC0_RX_ID (24)#define DDMA_ETHERNET_MAC0_TX_ID (25)#define DDMA_ETHERNET_MAC1_RX_ID (26)#define DDMA_ETHERNET_MAC1_TX_ID (27)#define DDMA_MEMORY_THROTTLE_ID (30)#define DDMA_MEMORY_ID (31)/* * Physical address of ddma peripherals */#define DDMA_UART0_TX_ADDR (0x11100004)#define DDMA_UART0_RX_ADDR (0x11100000)#define DDMA_UART3_TX_ADDR (0x11400004)#define DDMA_UART3_RX_ADDR (0x11400000)#define DDMA_USB_DEVICE_ENDPOINT_0_RX_ADDR (0x10200000)#define DDMA_USB_DEVICE_ENDPOINT_0_TX_ADDR (0x10200004)#define DDMA_USB_DEVICE_ENDPOINT_1_TX_ADDR (0x10200008)#define DDMA_USB_DEVICE_ENDPOINT_2_TX_ADDR (0x1020000C)#define DDMA_USB_DEVICE_ENDPOINT_3_RX_ADDR (0x10200010)#define DDMA_USB_DEVICE_ENDPOINT_4_RX_ADDR (0x10200014)#define DDMA_PSC0_TX_ADDR (0x11A0001C)#define DDMA_PSC0_RX_ADDR (0x11A0001C)#define DDMA_PSC1_TX_ADDR (0x11B0001C)#define DDMA_PSC1_RX_ADDR (0x11B0001C)#define DDMA_PSC2_TX_ADDR (0x10A0001C)#define DDMA_PSC2_RX_ADDR (0x10A0001C)#define DDMA_PSC3_TX_ADDR (0x10B0001C)#define DDMA_PSC3_RX_ADDR (0x10B0001C)/* * This structure allows the "driver" to keep track of local information. * It is not the actual CHANNEL structure, but it does contain a pointer * to the Au1550's DDMA channel it points to. */typedef void (*DDMA_CALLBACK)( void *channel, DDMA_DESCRIPTOR *head, int completed, void *arg );#define VIRT_TO_NXTPTR(x) (uint32)((KUSEG(x))>>5)// get the cacheabilty bits from the ring buffer OR in the shifted nxt_ptr#define NXTPTR_TO_VIRT(ring,pDesc) (DDMA_DESCRIPTOR*)( ((uint32)ring & KSEG_MSK) | ((uint32)(pDesc->u.std.nxt_ptr<<5)) )#define SRCPTR_TO_VIRT(ring,pDesc) (DDMA_DESCRIPTOR*)( ((uint32)ring & KSEG_MSK) | ((uint32)(pDesc->u.std.src_ptr)) )#define DSTPTR_TO_VIRT(ring,pDesc) (DDMA_DESCRIPTOR*)( ((uint32)ring & KSEG_MSK) | ((uint32)(pDesc->u.std.dst_ptr)) )typedef struct { DDMA_CHANNEL *ptr; // Pointer to physical channel int avail; // Available? int src_id,dst_id; // What peripheral is this connected to uint32 fifo_addr; // Addressof the device's fifo -- specific to dev_id int xfer_size; // Transfer size for dma requests DDMA_DESCRIPTOR *ring,*dh,*dt; // Descriptor ring/head/tail ptrs DDMA_CALLBACK callback; // User's Callback routine void *arg; // User's callback argument} CHANNEL;typedef struct{ DDMA_CALLBACK callback; void *arg; uint32 channel; // Requested channel void *descriptors; // Pointer to pre-allocated descriptors uint32 num_descriptors;// Number of descriptors that were allocated uint32 chan_cfg; // Channel configuration uint32 chan_irq; // Channel interrupt requests uint32 chan_stat; // Channel status register -- Physical address} CHANNEL_CONFIG;#endif⌨️ 快捷键说明
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