📄 ddma.h
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/********************************************************************* * * Copyright: * Advanced Micro Devices, AMD. All Rights Reserved. * You are hereby granted a copyright license to use, modify, and * distribute the SOFTWARE so long as this entire notice is * retained without alteration in any modified and/or redistributed * versions, and that such modified versions are clearly identified * as such. No licenses are granted by implication, estoppel or * otherwise under any patents or trademarks of AMD. This * software is provided on an "AS IS" basis and without warranty. * * To the maximum extent permitted by applicable law, AMD * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY * ACCOMPANYING WRITTEN MATERIALS. * * To the maximum extent permitted by applicable law, IN NO EVENT * SHALL AMD BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. * * AMD assumes no responsibility for the maintenance and support * of this software. ********************************************************************* * * File: ddma.h * * Purpose: Definitions for Au1550 DDMA * * $RCSfile: ddma.h,v $ * $Author: cgray $ * $Revision: 1.9 $ * $Date: 2003/12/22 21:20:21 $ ************************************************************************/#ifndef __AU1550_DDMA_#define __AU1550_DDMA_#define DDMA_PHYS_ADDRESS 0x14002000 // This is the base address for the first channel#define DDMA_NUM_CHANNELS 16 // general registers follow channels at 0x14003000#ifndef ASSEMBLERtypedef volatile struct{ uint32 cfg; // config uint32 des_ptr; // descriptor pointer uint32 stat_ptr; // status pointer uint32 db; // doorbell uint32 irq; // Interrupt uint32 status; // Status uint32 bytecnt; // Remaining byte count uint32 array[16]; // Debug Access uint8 reserved[0xA4]; // Padding to make channels line up on 0x100 boundry} DDMA_CHANNEL;#endif/* * Bit definitions for Channel Config */#define DDMA_CHANCFG_EN (1<<0)#define DDMA_CHANCFG_DBE (1<<1)#define DDMA_CHANCFG_SBE (1<<2)#define DDMA_CHANCFG_DFN (1<<3)#define DDMA_CHANCFG_PPR (1<<4)/* * Bit definitions for Channel Interrupt */#define DDMA_CHANINT_IN (1<<0)/* * Bit definitions for Channel Status */#define DDMA_CHANSTATUS_H (1<<0)#define DDMA_CHANSTATUS_V (1<<1)#define DDMA_CHANSTATUS_DB (1<<2)#ifndef ASSEMBLERtypedef volatile struct{ uint32 cmd; // Command uint32 byte_cnt; // Byte count uint32 src_ptr; // Source pointer uint32 src_strblk; // Source Stride/Block uint32 dst_ptr; // Destination pointer uint32 dst_strblk; // Destination stride/block uint32 stat; // Status / Subroutine pointer uint32 nxt_ptr; // next descriptor} DDMA_DESCRIPTOR_STD;#endif#ifndef ASSEMBLERtypedef volatile struct{ uint32 cmd; // Command uint32 byte_cnt; // Byte count uint32 src_data0; // Source data low uint32 src_data1; // Source data high uint32 dst_ptr; // Destination pointer uint32 dst_strblk; // Destination stride/block uint32 stat; // Status / Subroutine pointer uint32 nxt_ptr; // next descriptor} DDMA_DESCRIPTOR_WRITEDMA;#endif#ifndef ASSEMBLERtypedef volatile struct{ union { DDMA_DESCRIPTOR_STD std; DDMA_DESCRIPTOR_WRITEDMA wr; } u; //descriptor union union { uint8 u8[32]; uint16 u16[16]; uint32 u32[8]; void * p; }c; // context} DDMA_DESCRIPTOR;#endif/* * Bit definitions for descriptor command */#define DDMA_DESCCMD_ST (0 )#define DDMA_DESCCMD_ST_N(n) ((n&3)<<DDMA_DESCCMD_ST) #define DDMA_DESCCMD_ST_WRSTAT DDMA_DESCCMD_ST_N(1) #define DDMA_DESCCMD_ST_CLEAR DDMA_DESCCMD_ST_N(2) #define DDMA_DESCCMD_ST_WRCNT DDMA_DESCCMD_ST_N(3)#define DDMA_DESCCMD_CV (1<<2)#define DDMA_DESCCMD_RP (1<<3)#define DDMA_DESCCMD_SP (1<<4)#define DDMA_DESCCMD_NR (1<<5)#define DDMA_DESCCMD_SR (1<<6)#define DDMA_DESCCMD_SRS (1<<7)#define DDMA_DESCCMD_IE (1<<8) // Set interrupt bit upon completion#define DDMA_DESCCMD_RES (1<<9)#define DDMA_DESCCMD_SM (1<<10)#define DDMA_DESCCMD_DN (1<<11)#define DDMA_DESCCMD_SN (1<<12) #define DDMA_DESCCMD_DT (13) #define DDMA_DESCCMD_DT_N(n) ((n&3)<<DDMA_DESCCMD_DT) #define DDMA_DESCCMD_DT_REG DDMA_DESCCMD_DT_N(0) #define DDMA_DESCCMD_DT_WR DDMA_DESCCMD_DT_N(1) #define DDMA_DESCCMD_DT_COMPWR DDMA_DESCCMD_DT_N(2) #define DDMA_DESCCMD_DT_RES DDMA_DESCCMD_DT_N(3)#define DDMA_DESCCMD_ARB (1<<15)#define DDMA_DESCCMD_DW (16)#define DDMA_DESCCMD_DW_N(n) ((n&3)<<DDMA_DESCCMD_DW) #define DDMA_DESCCMD_DW_BYTE DDMA_DESCCMD_DW_N(0) #define DDMA_DESCCMD_DW_HWORD DDMA_DESCCMD_DW_N(1) #define DDMA_DESCCMD_DW_WORD DDMA_DESCCMD_DW_N(2)#define DDMA_DESCCMD_SW (18)#define DDMA_DESCCMD_SW_N(n) ((n&3)<<DDMA_DESCCMD_SW) #define DDMA_DESCCMD_SW_BYTE DDMA_DESCCMD_SW_N(0) #define DDMA_DESCCMD_SW_HWORD DDMA_DESCCMD_SW_N(1) #define DDMA_DESCCMD_SW_WORD DDMA_DESCCMD_SW_N(2)#define DDMA_DESCCMD_DID (20)#define DDMA_DESCCMD_DID_N(n) ((n&0x1F)<<DDMA_DESCCMD_DID)#define DDMA_DESCCMD_SID (25)#define DDMA_DESCCMD_SID_N(n) ((n&0x1F)<<DDMA_DESCCMD_SID)#define DDMA_DESCCMD_M (1<<30)#define DDMA_DESCCMD_V (1<<31)/* * Bit masks for descriptor count */#define DDMA_DESCCNT_BC (0)#define DDMA_DESCCNT_BC_N(n) ((n&0x1FFFF)<<DDMA_DESCCNT_BC)#define DDMA_DESCCNT_FL (22)#define DDMA_DESCCNT_FL_N(n) ((n&3)<<DDMA_DESCCNT_FL)#define DDMA_DESCCNT_DUPTR (24)#define DDMA_DESCCNT_DUPTR_N(n) ((n&4)<<DDMA_DESCCNT_DUPTR)#define DDMA_DESCCNT_SUPTR (28)#define DDMA_DESCCNT_SUPTR_N(n) ((n&4)<<DDMA_DESCCNT_SUPTR)/* * Bit definitions for source stride/block 1 dimensional */#define DDMA_DESCSRC_STRIDE_SS (0)#define DDMA_DESCSRC_STRIDE_SS_N(n) ((n&0x3fff)<<DDMA_DESCSRC_STRIDE_SS)#define DDMA_DESCSRC_STRIDE_SB (14)#define DDMA_DESCSRC_STRIDE_SB_N(n) ((n&0x3Fff)<<DDMA_DESCSRC_STRIDE_SB)#define DDMA_DESCSRC_STRIDE_SAM (28)#define DDMA_DESCSRC_STRIDE_SAM_N(n) ((n&3)<<DDMA_DESCSRC_STRIDE_SAM) #define DDMA_DESCSRC_STRIDE_SAM_INC DDMA_DESCSRC_STRIDE_SAM_N(0) #define DDMA_DESCSRC_STRIDE_SAM_DEC DDMA_DESCSRC_STRIDE_SAM_N(1) #define DDMA_DESCSRC_STRIDE_SAM_STATIC DDMA_DESCSRC_STRIDE_SAM_N(2) #define DDMA_DESCSRC_STRIDE_SAM_BURST DDMA_DESCSRC_STRIDE_SAM_N(3)#define DDMA_DESCSRC_STRIDE_STS (30)#define DDMA_DESCSRC_STRIDE_STS_N(n) ((n&3)<<DDMA_DESCSRC_STRIDE_STS) #define DDMA_DESCSRC_STRIDE_STS_1 DDMA_DESCSRC_STRIDE_STS_N(0) #define DDMA_DESCSRC_STRIDE_STS_2 DDMA_DESCSRC_STRIDE_STS_N(1) #define DDMA_DESCSRC_STRIDE_STS_4 DDMA_DESCSRC_STRIDE_STS_N(2) #define DDMA_DESCSRC_STRIDE_STS_8 DDMA_DESCSRC_STRIDE_STS_N(3) /* * Bit definitions for source stride/block 2 dimensional */#define DDMA_DESCSRC_STRIDE2DIM_SC (0)#define DDMA_DESCSRC_STRIDE2DIM_SC_N(n) ((n&0x3ff)<<DDMA_DESCSRC_STRIDE2DIM_SC)#define DDMA_DESCSRC_STRIDE2DIM_SS (11)#define DDMA_DESCSRC_STRIDE2DIM_SS_N(n) ((n&0x1ff)<<DDMA_DESCSRC_STRIDE2DIM_SS)#define DDMA_DESCSRC_STRIDE2DIM_SB (21)#define DDMA_DESCSRC_STRIDE2DIM_SB_N(n) ((n&0x07f)<<DDMA_DESCSRC_STRIDE2DIM_SB)⌨️ 快捷键说明
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