pci.h

嵌入式linux（arm9）的平台下

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 *
 * Copyright:
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 *********************************************************************
 *
 * File:		pci.h
 *
 * Purpose:		Definitions for Au1550 PCI
 *
 *  $RCSfile: pci.h,v $
 *  $Author: kkosiek $
 *  $Revision: 1.3 $
 *  $Date: 2004/01/13 22:21:32 $
 *
***********************************************************************/

#define	PCI_PHYS_ADDRESS	0x014005000		//Physical Base Address	

/*
 * PCI Register Offsets
 */

#define PCI_CMEM				(0x0000)
#define PCI_CONFIG				(0x0004)
#define PCI_B2BMASK_CCH			(0x0008)
#define PCI_B2BBASE0_VENID		(0x000C)
#define PCI_B2BBASE1_SUBID		(0x0010)
#define PCI_MWMASK_DEV			(0x0014)
#define PCI_MWBASE_REV_CCL		(0x0018)
#define PCI_ERR_ADDR			(0x001C)
#define PCI_SPEC_INTACK			(0x0020)
#define PCI_PR_CONFIG			(0x0024)
#define PCI_PR_ADDR				(0x0028)
#define PCI_PR_STS				(0x002C)
//#define PCI_PR_DATA	this register is programmable through PR_ADDR & PR_CONFIG
#define PCI_ID					(0x0100)
#define PCI_STATCMD				(0x0104)
#define PCI_CLASSREV			(0x0108)
#define PCI_PARAM				(0x010C)
#define PCI_MBAR				(0x0110)
#define PCI_TIMEOUT				(0x0140)

typedef volatile struct
{
	uint32 cmem;
	uint32 config;
	uint32 b2bmask_cch;
	uint32 b2bbase0_venid;
	uint32 b2bbase1_subid;
	uint32 mwmask_dev;
	uint32 mwbase_rev_ccl;
	uint32 err_addr;
	uint32 spec_intack;
	uint32 pr_config;
	uint32 pr_addr;
	uint32 pr_sts;				  //offset at 0x2C
	uint32 reserved[(0x0100-0x0030)/4];//uint8  reserved[0xD0];
	uint32 id;
	uint32 statcmd;
	uint32 classrev;
	uint32 param;
	uint32 mbar;				//offset at 0x110
	uint8  reserved1[0x2C];		//pad space so timeout offset is at 0x140
	uint32 timeout;

} AU1550_PCI;

/* PCI cacheable memory region register bit offsets */

#define PCI_CMEM_HC				(1<<31)
#define PCI_CMEM_E				(1<<28)
#define PCI_CMEM_CMBASE			(0x3FFF<<14)
#define PCI_CMEM_CMMASK			(0x3FFF<<0)

/* PCI configuration register bit offsets */

#define PCI_CONFIG_ERRADDR		(0xF<<28)
#define PCI_CONFIG_ERD			(1<<27)
#define PCI_CONFIG_ET			(1<<26)
#define PCI_CONFIG_EF			(1<<25)
#define PCI_CONFIG_EP			(1<<24)
#define PCI_CONFIG_EM			(1<<23)
#define PCI_CONFIG_BM			(1<<22)
#define PCI_CONFIG_PD			(1<<20)
#define PCI_CONFFIG_BME			(1<<19)
#define PCI_CONFIG_NC			(1<<16)
#define PCI_CONFIG_IA			(1<<15)
#define PCI_CONFIG_IP			(1<<13)
#define PCI_CONFIG_IS			(1<<12)
#define PCI_CONFIG_IMM			(1<<11)
#define PCI_CONFIG_ITM			(1<<10)
#define PCI_CONFIG_ITT			(1<<9)
#define PCI_CONFIG_IPB			(1<<8)
#define PCI_CONFIG_SIC			(3<<6)
#define PCI_CONFIG_ST			(1<<5)
#define PCI_CONFIG_SM			(1<<4)
#define PCI_CONFIG_AEN			(1<<3)
#define PCI_CONFIG_R2H			(1<<2)
#define PCI_CONFIG_R1H			(1<<1)
#define PCI_CONFIG_CH			(1<<0)

/* PCI Back to Back Mask/Class Code High Register bit offsets */

#define PCI_B2BMASK_CCH_B2BMASK	(0xFFFF<<16)
#define PCI_B2BMASK_CCH_CCH		(0xFFFF<<0)

/* PCI Back to Back Base Zero Register bit offsets */

#define PCI_B2BBASE0_VENID_B2BBASE0	(0xFFFF<<16)
#define PCI_B2BBASE0_VENID_SVID		(0xFFFF<<0)

/* PCI Back to Back Base 0ne Register bit offsets */

#define PCI_B2BBASE1_SUBID_B2BBASE1	(0xFFFF<<16)
#define PCI_B2BBASE1_SUBID_SUBID	(0xFFFF<<0)

/* PCI Memory Window Mask/Device ID Register bit offsets */

#define PCI_MWMASK_DEV_MWMASK		(0xFFFF<<16)
#define PCI_MWMASK_DEV_DEVID		(0xFFFF<<0)

/* PCI Memory Window Base/Revision/Class Code Low Register bit offsets */

#define PCI_MWBASE_REV_CCL_MWBASE	(0xFFFF<<16)
#define PCI_MWBASE_REV_CCL_REVID	(0xFF<<8)
#define PCI_MWBASE_REV_CCL_CCL		(0xFF<<0)

/* PCI Posted Read Configuration bit offsets */

#define	PCI_PR_AM			(1<<9)
#define	PCI_PR_DM			(1<<8)
#define PCI_PR_BS			(0x7<<4)
#define	PCI_PR_ADDR_HIGH	(0xf<<0)

/* PCI Posted Read Status bit offsets*/

#define	PCI_PR_AI			(1<<9)
#define PCI_PR_DI			(1<<8)
#define	PCI_PR_PND			(1<<0)
								 
/* PCI Device/Vendor ID bit offsets */

#define	PCI_ID_DID			(0xffff<<16)
#define PCI_ID_VID			(0xffff<<0)

/* PCI Status and Command bit offsets */

#define PCI_STATCMD_STATUS	(0xffff<<16)
#define PCI_STATCMD_CMD		(0xffff<<0)

/* PCI Class and Revision bit offsets */

#define PCI_CLASSREV_CLASS	(0xffffff<<8)
#define PCI_CLASSREV_REV	(0xff<<0)

/* PCI Parameter bit offsets */

#define PCI_PARAM_BIST		(0xff<<24)
#define	PCI_PARAM_HT		(0xff<<16)
#define PCI_PARAM_LT		(0xff<<8)
#define PCI_PARAM_CLS		(0xff<<0)

/* PCI Configuration Timeout bit offsets */

#define PCI_TIMEOUT_TR		(0xfff<<16)
#define PCI_TIMEOUT_MR		(0xff<<8)  
#define PCI_TIMEOUT_TO		(0xff<<0)