platform.h

嵌入式linux（arm9）的平台下

#ifndef DB1200
#define DB1200
#endif
#define AU1200

/*
 * Frequency info
 */
#define CPU_FREQUENCY	(12000000 * 33)
#define CPU_SD		2


#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
/* SPI and SMB are muxed on the Db1200 board.
   Refer to board documentation.
 */
#define SPI_PSC_BASE        PSC0_PHYS_ADDR
#define SMBUS_PSC_BASE      PSC0_PHYS_ADDR
/* AC97 and I2S are muxed on the Db1200 board.
   Refer to board documentation.
 */
#define AC97_PSC_BASE       PSC1_PHYS_ADDR
#define I2S_PSC_BASE        PSC1_PHYS_ADDR

#define BCSR_PHYS_ADDR 0x19800000

#ifndef ASSEMBLER
typedef volatile struct
{
	/*00*/	uint16 whoami;
			uint16 reserved0;
	/*04*/	uint16 status;
			uint16 reserved1;
	/*08*/	uint16 switches;
			uint16 reserved2;
	/*0C*/	uint16 resets;
			uint16 reserved3;

	/*10*/	uint16 pcmcia;
			uint16 reserved4;
	/*14*/	uint16 board;
			uint16 reserved5;
	/*18*/	uint16 disk_leds;
			uint16 reserved6;
	/*1C*/	uint16 system_control;
			uint16 reserved7;

	/*20*/	uint16 intclr;
			uint16 reserved8;
	/*24*/	uint16 intset;
			uint16 reserved9;
	/*28*/	uint16 intclr_mask;
			uint16 reserved10;
	/*2C*/	uint16 intset_mask;
			uint16 reserved11;

	/*30*/	uint16 sig_status;
			uint16 reserved12;
	/*34*/	uint16 int_status;
			uint16 reserved13;
	/*38*/	uint16 reserved14;
			uint16 reserved15;
	/*3C*/	uint16 reserved16;
			uint16 reserved17;

} BCSR;

static BCSR* bcsr = (BCSR*) KSEG1(BCSR_PHYS_ADDR);
#endif

/*
 * Register bit definitions for the BCSRs  */
#define BCSR_WHOAMI_DCID		0x000F
#define BCSR_WHOAMI_CPLD		0x00F0
#define BCSR_WHOAMI_BOARD		0x0F00

#define BCSR_STATUS_PCMCIA0VS		0x0003
#define BCSR_STATUS_PCMCIA1VS		0x000C
#define BCSR_STATUS_SWAPBOOT		0x0040
#define BCSR_STATUS_FLASHBUSY		0x0100
#define BCSR_STATUS_IDECBLID		0x0200
#define BCSR_STATUS_SD0WP		0x0400
#define BCSR_STATUS_U0RXD		0x1000
#define BCSR_STATUS_U1RXD		0x2000
#define PCMCIA_PC0_VS(X)		((X&BCSR_STATUS_PCMCIA0VS)>>0)
#define PCMCIA_PC1_VS(X)		((X&BCSR_STATUS_PCMCIA1VS)>>2)

#define BCSR_SWITCHES_OCTAL		0x00FF
#define BCSR_SWITCHES_DIP_1		0x0080
#define BCSR_SWITCHES_DIP_2		0x0040
#define BCSR_SWITCHES_DIP_3		0x0020
#define BCSR_SWITCHES_DIP_4		0x0010
#define BCSR_SWITCHES_DIP_5		0x0008
#define BCSR_SWITCHES_DIP_6		0x0004
#define BCSR_SWITCHES_DIP_7		0x0002
#define BCSR_SWITCHES_DIP_8		0x0001
#define BCSR_SWITCHES_ROTARY		0x0F00

#define BCSR_RESETS_ETH			0x0001
#define BCSR_RESETS_CAMERA		0x0002
#define BCSR_RESETS_DC			0x0004
#define BCSR_RESETS_IDE			0x0008
#define BCSR_RESETS_TV			0x0010
/* not resets but in the same register */ 
#define BCSR_RESETS_PWM1MUX		0x0800
#define BCSR_RESETS_PCS0MUX		0x1000
#define BCSR_RESETS_PCS1MUX		0x2000
#define BCSR_RESETS_SPISEL		0x4000

#define BCSR_PCMCIA_PC0VPP		0x0003
#define BCSR_PCMCIA_PC0VCC		0x000C
#define BCSR_PCMCIA_PC0DRVEN		0x0010
#define BCSR_PCMCIA_PC0RST		0x0080
#define BCSR_PCMCIA_PC1VPP		0x0300
#define BCSR_PCMCIA_PC1VCC		0x0C00
#define BCSR_PCMCIA_PC1DRVEN		0x1000
#define BCSR_PCMCIA_PC1RST		0x8000
#define BCSR_PCMCIA_PC0VPP_N(N)	(BCSR_PCMCIA_PC0VPP & (N<<0))
#define BCSR_PCMCIA_PC0VCC_N(N)	(BCSR_PCMCIA_PC0VCC & (N<<2))
#define BCSR_PCMCIA_PC1VPP_N(N)	(BCSR_PCMCIA_PC1VPP & (N<<8))
#define BCSR_PCMCIA_PC1VCC_N(N)	(BCSR_PCMCIA_PC1VCC & (N<<10))

#define BCSR_BOARD_LCDVEE		0x0001
#define BCSR_BOARD_LCDVDD		0x0002
#define BCSR_BOARD_LCDBL		0x0004
#define BCSR_BOARD_CAMSNAP		0x0010
#define BCSR_BOARD_CAMPWR		0x0020
#define BCSR_BOARD_SD0PWR		0x0040

#define BCSR_LEDS_DECIMALS		0x0003
#define BCSR_LEDS_LED0			0x0100
#define BCSR_LEDS_LED1			0x0200
#define BCSR_LEDS_LED2			0x0400
#define BCSR_LEDS_LED3			0x0800

#define BCSR_SYSTEM_POWEROFF		0x4000
#define BCSR_SYSTEM_RESET		0x8000

#define BCSR_SIGSTAT_IDEIRQ		0x0001
#define BCSR_SIGSTAT_ETHERNETIRQ	0x0002
#define BCSR_SIGSTAT_PC0IRQ		0x0004
#define BCSR_SIGSTAT_PC0STSCHG		0x0008
#define BCSR_SIGSTAT_PC1IRQ		0x0010
#define BCSR_SIGSTAT_PC1STSCHG		0x0020
#define BCSR_SIGSTAT_DCIRQ		0x0040
#define BCSR_SIGSTAT_FLASHBUSY		0x0080
#define BCSR_SIGSTAT_PCMCIA0DET		0x0100
#define BCSR_SIGSTAT_PCMCIA1DET		0x0400
#define BCSR_SIGSTAT_SD0DET		0x1000

/* Bit positions for the different interrupt sources */
#define BCSR_INT_IDE			0x0001
#define BCSR_INT_ETH			0x0002
#define BCSR_INT_PC0			0x0004
#define BCSR_INT_PC0STSCHG		0x0008
#define BCSR_INT_PC1			0x0010
#define BCSR_INT_PC1STSCHG		0x0020
#define BCSR_INT_DC			0x0040
#define BCSR_INT_FLASHBUSY		0x0080
#define BCSR_INT_PC0INSERT		0x0100
#define BCSR_INT_PC0EJECT		0x0200
#define BCSR_INT_PC1INSERT		0x0400
#define BCSR_INT_PC1EJECT		0x0800
#define BCSR_INT_SD0INSERT		0x1000
#define BCSR_INT_SD0EJECT		0x2000

#define AU1X00_EXTERNAL_INT		AU1000_GPIO_7

/* SMSC LAN91C111 */
#define AU1XXX_SMC91111_BASE		(0xA9000000)
#define AU1XXX_SMC91111_END		(0xA97FFFFF)
#define AU1XXX_SMC91111_MEM_SIZE	(AU1XXX_SMC91111_END - AU1XXX_SMC91111_BASE + 1)
// shared IRQs
#define AU1XXX_SMC91111_IRQ		AU1X00_EXTERNAL_INT

/* DC_IDE and DC_ETHERNET */
#define AU1XXX_ATA_BASE			(0xA8800000)
#define AU1XXX_ATA_END			(0xA8FFFFFF)
#define AU1XXX_ATA_MEM_SIZE		(AU1XXX_ATA_END - AU1XXX_ATA_BASE +1)

#define AU1XXX_ATA_REG_OFFSET		(5)
#define AU1XXX_SMC91111_OFFSET		(0x300)

#define IDE_PHYS_ADDR			0x18800000

//#define NAND_PHYS_ADDR   0x1C000000

#define PCMCIA_MAX_SOCK			1
#define PCMCIA_NUM_SOCKS		(PCMCIA_MAX_SOCK+1)

#define SD_MAX_SLOT			0
#define SD_NUM_SLOTS			(SD_MAX_SLOT+1)

#define PCMCIA_PC_IRQ			7
#define PCMCIA_PC0_IRQ			PCMCIA_PC_IRQ
#define PCMCIA_PC1_IRQ			PCMCIA_PC_IRQ
#define PCMCIA_CARD_COUNT		2


#define FLASH_AMD_MIRRORBIT
#define FLASH_START_PHYS_ADDRESS	0x1E000000
#define FLASH_END_PHYS_ADDRESS		0x1FFFFFFF
#define FLASH_BLOCK_SIZE		0x00020000
#define FLASH_ALTERNATE_ADDR		0xBDC00000

#define NAND_FORCE_CE_GPIO		215