rtcodeccomm.cpp

freesacle mx21下的声卡alc5620的驱动程序

		Enable_Main_Spatial(TRUE);

		//set parameter a1 support 48K	
		if(KHZ48_000==m_WaveOutSampleRate)
		{				
			bRetVal=WriteCodecRegMask(RT_PSEDUEO_SPATIAL_CTRL,APF_FOR_48K,APF_MASK);
		}
		else if(KHZ44_100==m_WaveOutSampleRate)//set parameter a1 support 44.1K	
		{
			bRetVal=WriteCodecRegMask(RT_PSEDUEO_SPATIAL_CTRL,APF_FOR_44_1K,APF_MASK);
		}
		else
		{
			//set parameter a1 support 32k and lower	
			bRetVal=WriteCodecRegMask(RT_PSEDUEO_SPATIAL_CTRL,APF_FOR_32K,APF_MASK);
		}	

		//Enable All Pass Filter 
		bRetVal=WriteCodecRegMask(RT_PSEDUEO_SPATIAL_CTRL,ALL_PASS_FILTER_EN,ALL_PASS_FILTER_EN);
	}
	else
	{
		//Disable All Pass Filter
		bRetVal=WriteCodecRegMask(RT_PSEDUEO_SPATIAL_CTRL,0,ALL_PASS_FILTER_EN);
	}

	return bRetVal;
}
//*****************************************************************************
//
//function:Enable/Disable ADC input source control
//
//*****************************************************************************
BOOL RT_CodecComm::Enable_ADC_Input_Source(ADC_INPUT_MIXER_CTRL ADC_Input_Sour,BOOL Enable)
{
	BOOL bRetVal=FALSE;
	
	if(Enable)
	{
		//Enable ADC source 
		bRetVal=WriteCodecRegMask(RT_ADC_RECORD_MIXER,0,ADC_Input_Sour);
	}
	else
	{
		//Disable ADC source		
		bRetVal=WriteCodecRegMask(RT_ADC_RECORD_MIXER,ADC_Input_Sour,ADC_Input_Sour);
	}

	return bRetVal;
}

//*****************************************************************************
//
//function:Enable/Disable Auto Volume Control function
//
//*****************************************************************************
BOOL RT_CodecComm::EnableAVC(BOOL Enable_AVC)
{
	BOOL bRetVal=FALSE;
	
	if(Enable_AVC)
	{			
		//enable AVC target select,if use voice interface,please use one channel 
		WriteCodecRegMask(RT_MISC_CTRL,AVC_TARTGET_SEL_BOTH,AVC_TARTGET_SEL_MASK); 

		//Enable AVC function
		bRetVal=WriteCodecAdvanceMask(AVC_CTRL_REG0,ENABLE_AVC_GAIN_CTRL,ENABLE_AVC_GAIN_CTRL);
		
	}
	else
	{
		//Disable AVC function
		bRetVal=WriteCodecAdvanceMask(AVC_CTRL_REG0,0,ENABLE_AVC_GAIN_CTRL);
	}

	return bRetVal;
}
//*****************************************************************************
//
//function:Config Vmid Control function
//
//			 AVDD  		HPVDD 	SPKVDD	SPK AB		SPK D		HP		
//case 1	 3.3V		3.3V	3.3V	1.00 Vdd	1.00 Vdd	1.00 Vdd	
//case 2	 3.3V		3.3V	4.2V	1.25 Vdd	1.25 Vdd	1.00 Vdd
//case 3	 2.5V		3.3V	3.3V	1.25 Vdd	1.25 Vdd	1.25 Vdd
//case 4	 2.5V		3.3V	4.2V	1.75 Vdd	1.75 Vdd	1.25 Vdd
//
//*****************************************************************************
BOOL RT_CodecComm::ConfigVmidOutput(BYTE Vmid_CaseType)
{

	BOOL bRetVal=FALSE;



	switch(Vmid_CaseType)
	{
		case 1:
			bRetVal=WriteCodecRegMask(
										RT_GEN_CTRL_REG1,
										(GP_HP_AMP_CTRL_RATIO_100	 |
										 GP_SPK_D_AMP_CTRL_RATIO_100 |
										 GP_SPK_AB_AMP_CTRL_RATIO_100)	
										,
										(GP_HP_AMP_CTRL_MASK		|
										GP_SPK_D_AMP_CTRL_MASK		|
										GP_SPK_AB_AMP_CTRL_MASK)
									 );
			break;

		case 2:
			bRetVal=WriteCodecRegMask(
										RT_GEN_CTRL_REG1,
										(GP_HP_AMP_CTRL_RATIO_100	 |
										 GP_SPK_D_AMP_CTRL_RATIO_125 |
										 GP_SPK_AB_AMP_CTRL_RATIO_125)	
										,
										(GP_HP_AMP_CTRL_MASK		|
										GP_SPK_D_AMP_CTRL_MASK		|
										GP_SPK_AB_AMP_CTRL_MASK)
									 );
			break;

		case 3:
			bRetVal=WriteCodecRegMask(
										RT_GEN_CTRL_REG1,
										(GP_HP_AMP_CTRL_RATIO_125	 |
										 GP_SPK_D_AMP_CTRL_RATIO_125 |
										 GP_SPK_AB_AMP_CTRL_RATIO_125)	
										,
										(GP_HP_AMP_CTRL_MASK		|
										GP_SPK_D_AMP_CTRL_MASK		|
										GP_SPK_AB_AMP_CTRL_MASK)
									 );
			break;

		case 4:
			bRetVal=WriteCodecRegMask(
										RT_GEN_CTRL_REG1,
										(GP_HP_AMP_CTRL_RATIO_125	 |
										 GP_SPK_D_AMP_CTRL_RATIO_175 |
										 GP_SPK_AB_AMP_CTRL_RATIO_175)	
										,
										(GP_HP_AMP_CTRL_MASK		|
										GP_SPK_D_AMP_CTRL_MASK		|
										GP_SPK_AB_AMP_CTRL_MASK)
									 );
			break;

		default:
			return  FALSE;
	}
	return bRetVal;
}

//*****************************************************************************
//
//function:Config Microphone BIAS function
//
//*****************************************************************************
BOOL RT_CodecComm::ConfigMicBias(BYTE Mic,BYTE MicBiasCtrl)
{
	BOOL bRetVal=FALSE;

	if(Mic==MIC1)
	{
		if(MicBiasCtrl==MIC_BIAS_90_PRECNET_AVDD)
		  {	
			bRetVal=WriteCodecRegMask(RT_MICROPHONE_CTRL,MIC1_BIAS_VOLT_CTRL_90P,MIC1_BIAS_VOLT_CTRL_MASK);
		  }
		 else if(MicBiasCtrl==MIC_BIAS_75_PRECNET_AVDD)
		  {	
			bRetVal=WriteCodecRegMask(RT_MICROPHONE_CTRL,MIC1_BIAS_VOLT_CTRL_75P,MIC1_BIAS_VOLT_CTRL_MASK);
		  }			
	}
	else if(Mic==MIC2)
	{
		if(MicBiasCtrl==MIC_BIAS_90_PRECNET_AVDD)
		  {	
			bRetVal=WriteCodecRegMask(RT_MICROPHONE_CTRL,MIC2_BIAS_VOLT_CTRL_90P,MIC2_BIAS_VOLT_CTRL_MASK);
		  }
		 else if(MicBiasCtrl==MIC_BIAS_75_PRECNET_AVDD)
		  {	
			bRetVal=WriteCodecRegMask(RT_MICROPHONE_CTRL,MIC2_BIAS_VOLT_CTRL_75P,MIC2_BIAS_VOLT_CTRL_MASK);
		  }		
	}
	
	return 	bRetVal;
}

//*****************************************************************************
//function:Enable the Voice PCM interface Path
//*****************************************************************************

BOOL RT_CodecComm::ConfigPcmVoicePath(BOOL bEnableVoicePath,MODE_SEL mode)
{
	BOOL bRetVal=FALSE;

	if(bEnableVoicePath)
	 {

		switch(mode)		
		{
			case MASTER_MODE_A:	//8kHz sampling rate,32 bits PCM and master mode,MCLK=24.576MHz.

				//Enable GPIO 1,3,4,5 to voice interface
				//Set I2S to Master mode
				//Set voice i2s VBCLK Polarity to Invert
				//Set PCM mode to Mode A
				//Set Data length to 16 bit
				//set Data Fomrat to PCM format

				bRetVal=WriteCodecRegMask(RT_EXTEND_SDP_CTRL,
										  (EXT_I2S_FUNC_ENABLE  	|								
										   EXT_I2S_BCLK_POLARITY	|
										   EXT_I2S_DL_16  	   		|			
										   EXT_I2S_DF_PCM),
								  			(EXT_I2S_FUNC_ENABLE 	|	
								   			EXT_I2S_MODE_SEL    	|
						   		   			EXT_I2S_BCLK_POLARITY	|
				    			   		   EXT_I2S_PCM_MODE    		|	
								   		   EXT_I2S_DL_MASK 	   		|
						   				   EXT_I2S_DF_MASK)	
											);
				if(!bRetVal)
					goto exit;	

				//Set Voice MCLK from MCLK input
				//set Voice SYSCLK from  MCLK
				//set voice WCLK select divide 32
				//set voice SCLK select divide 3 and 32 

				bRetVal=WriteCodecRegMask(RT_VOICE_DAC_PCMCLK_CTRL1,
										  (VOICE_MCLK_SEL_MCLK_INPUT  	|	
											VOICE_SYSCLK_SEL_MCLK		|										
										   VOICE_WCLK_DIV_32			|
										   VOICE_SCLK_DIV1_3   			|			
						   					VOICE_SCLK_DIV2_32),
										  (VOICE_MCLK_SEL_MASK		 	|	
										   VOICE_SYSCLK_SEL_MASK   		|
						   				   VOICE_WCLK_DIV_MASK			|
						   				   VOICE_SCLK_DIV1_MASK    		|	
						   				   VOICE_SCLK_DIV2_MASK)	
										);
				if(!bRetVal)
					goto exit;

				//set Voice filter clock source from MCLK
				//set Voice AD/DA filter select 64X
				//set Voice DA/AD Sigma_Delta_clock source from DA Filter
				//set Voice CLK filter Div 3 and 16

				WriteCodecRegMask(RT_VOICE_DAC_PCMCLK_CTRL2,
								  (VOICE_FILTER_CLK_F_MCLK  	|								
								   VOICE_AD_DA_FILTER_SEL_64X	|
						   		   VOICE_AD_DA_SIG_CLK_F_DA_F	|		
						   		   VOICE_CLK_FILTER_DIV2_3		|
						   		   VOICE_CLK_FILTER_DIV1_16),
						  		  (VOICE_FILTER_CLK_F_MASK	 	|	
						   		   VOICE_AD_DA_FILTER_SEL_MASK	|
						   		   VOICE_AD_DA_SIG_CLK_F_DA_MASK|
						   		   VOICE_CLK_FILTER_DIV2_MASK	|	
						   		   VOICE_CLK_FILTER_DIV1_MASK)	
									);
				if(!bRetVal)
					goto exit;

		
				break;
		

			case MASTER_MODE_B://8018.2Hz sampling rate,32 bits PCM and master mode,MCLK=22.5792MHz.

				//Enable GPIO 1,3,4,5 to voice interface
				//Set I2S to Master mode
				//Set voice i2s VBCLK Polarity to Invert
				//Set PCM mode to Mode A
				//Set Data length to 16 bit
				//set Data Fomrat to PCM format

				bRetVal=WriteCodecRegMask(RT_EXTEND_SDP_CTRL,
										  (EXT_I2S_FUNC_ENABLE  	|								
										   EXT_I2S_BCLK_POLARITY	|
										   EXT_I2S_DL_16  	   		|			
										   EXT_I2S_DF_PCM),
								  			(EXT_I2S_FUNC_ENABLE 	|	
								   			EXT_I2S_MODE_SEL    	|
						   		   			EXT_I2S_BCLK_POLARITY	|
				    			   		   EXT_I2S_PCM_MODE    		|	
								   		   EXT_I2S_DL_MASK 	   		|
						   				   EXT_I2S_DF_MASK)	
											);
				if(!bRetVal)
					goto exit;	

				//Set Voice MCLK from MCLK input
				//set Voice SYSCLK from  MCLK
				//set voice WCLK select divide 32
				//set voice SCLK select divide 11 and 8 

				bRetVal=WriteCodecRegMask(RT_VOICE_DAC_PCMCLK_CTRL1,
										  (VOICE_MCLK_SEL_MCLK_INPUT  	|	
											VOICE_SYSCLK_SEL_MCLK		|										
										   VOICE_WCLK_DIV_32			|
										   VOICE_SCLK_DIV1_11  			|			
						   					VOICE_SCLK_DIV2_8),
										  (VOICE_MCLK_SEL_MASK		 	|	
										   VOICE_SYSCLK_SEL_MASK   		|
						   				   VOICE_WCLK_DIV_MASK			|
						   				   VOICE_SCLK_DIV1_MASK    		|	
						   				   VOICE_SCLK_DIV2_MASK)	
										);
				if(!bRetVal)
					goto exit;

				//set Voice filter clock source from MCLK
				//set Voice AD/DA filter select 64X
				//set Voice DA/AD Sigma_Delta_clock source from DA Filter
				//set Voice CLK filter Div 11 and 4

				WriteCodecRegMask(RT_VOICE_DAC_PCMCLK_CTRL2,
								  (VOICE_FILTER_CLK_F_MCLK  	|								
								   VOICE_AD_DA_FILTER_SEL_64X	|
						   		   VOICE_AD_DA_SIG_CLK_F_DA_F	|		
						   		   VOICE_CLK_FILTER_DIV2_11		|
						   		   VOICE_CLK_FILTER_DIV1_4),
						  		  (VOICE_FILTER_CLK_F_MASK	 	|	
						   		   VOICE_AD_DA_FILTER_SEL_MASK	|
						   		   VOICE_AD_DA_SIG_CLK_F_DA_MASK|
						   		   VOICE_CLK_FILTER_DIV2_MASK	|	
						   		   VOICE_CLK_FILTER_DIV1_MASK)	
									);
				if(!bRetVal)
					goto exit;

		
				break;
			 
			case SLAVE_MODE: //8KHz sample rate,32bit PCM format,slave mode with 256fs EXTCLK

				//Enable GPIO 1,3,4,5 to voice interface
				//Set I2S to slave mode
				//Set voice i2s VBCLK Polarity to Invert
				//Set PCM mode to Mode A
				//Set Data length to 16 bit
				//set Data Fomrat to PCM format

				bRetVal=WriteCodecRegMask(RT_EXTEND_SDP_CTRL,
										  (EXT_I2S_FUNC_ENABLE  	|
										   EXT_I2S_MODE_SEL    		|								
										   EXT_I2S_BCLK_POLARITY	|
										   EXT_I2S_DL_16  	   		|			
										   EXT_I2S_DF_PCM),
								  		   (EXT_I2S_FUNC_ENABLE	 	|	
								   			EXT_I2S_MODE_SEL   		|
						   		   			EXT_I2S_BCLK_POLARITY	|
				    			   		   EXT_I2S_PCM_MODE    		|	
								   		   EXT_I2S_DL_MASK 	   		|
						   				   EXT_I2S_DF_MASK)	
											);
				if(!bRetVal)
					goto exit;	

				//Set Voice MCLK from MCLK input
				//set Voice SYSCLK from  EXTCLK

				bRetVal=WriteCodecRegMask(RT_VOICE_DAC_PCMCLK_CTRL1,
										  (VOICE_MCLK_SEL_MCLK_INPUT  	|								
											VOICE_SYSCLK_SEL_EXTCLK
											),
										  (VOICE_MCLK_SEL_MASK		 	|	
										   VOICE_SYSCLK_SEL_MASK   		
											)	
										);
				if(!bRetVal)
					goto exit;

				//set Voice filter clock source from MCLK
				//set Voice AD/DA filter select 64X
				//set Voice DA/AD Sigma_Delta_clock source from DA Filter
				//set Voice CLK filter Div 2 and 2

				bRetVal=WriteCodecRegMask(RT_VOICE_DAC_PCMCLK_CTRL2,
										  (VOICE_FILTER_CLK_F_MCLK  	|								
										   VOICE_AD_DA_FILTER_SEL_64X	|
						   				   VOICE_AD_DA_SIG_CLK_F_DA_F	|		
						   				   VOICE_CLK_FILTER_DIV2_2		|
						   				   VOICE_CLK_FILTER_DIV1_2),
						  				  (VOICE_FILTER_CLK_F_MASK	 	|	
						   				   VOICE_AD_DA_FILTER_SEL_MASK	|
						   				   VOICE_AD_DA_SIG_CLK_F_DA_MASK|
						   				   VOICE_CLK_FILTER_DIV2_MASK	|	
						   				   VOICE_CLK_FILTER_DIV1_MASK)	
										);
				if(!bRetVal)
					goto exit;

				break;

			default:
				//do nothing		
				break;

			}
		}
 		else
		{
			//Disable Voice PCM interface	
			WriteCodecRegMask(RT_EXTEND_SDP_CTRL,0,EXT_I2S_FUNC_ENABLE);
		}
	
exit:	
	return bRetVal;
}
//*****************************************************************************
//function:Enable the PLL function
//*****************************************************************************
BOOL RT_CodecComm::EnablePLLPath(BOOL bEnablePLL)
{	
	unsigned short int usRegVal;
	BOOL bRetVal=FALSE;

	if(bEnablePLL)
	  {
		//48K,MCLK=13MHz,Fout=24.555MHz,N=66,M=7,K=2
		usRegVal=PLL_CTRL_M_VAL(7) | PLL_CTRL_K_VAL(2) |PLL_CTRL_N_VAL(66);
		bRetVal=ShadowWriteCodec(RT_PLL_CTRL,usRegVal,CodecDevId);

		//codec clock source from PLL output		
		bRetVal=WriteCodecRegMask(RT_GEN_CTRL_REG1,GP_CLK_FROM_PLL,GP_CLK_FROM_PLL);
		
		//Disable PLL Power		
		bRetVal=WriteCodecRegMask(RT_PWR_MANAG_ADD2,0,PWR_PLL);	
		//Enable PLL Power
		bRetVal=WriteCodecRegMask(RT_PWR_MANAG_ADD2,PWR_PLL,PWR_PLL);	
	  }
	else
	  {
		//codec clock source from MCLK output		
		bRetVal=WriteCodecRegMask(RT_GEN_CTRL_REG1,0,GP_CLK_FROM_PLL);		
		//Disable PLL Power
		bRetVal=WriteCodecRegMask(RT_PWR_MANAG_ADD2,0,PWR_PLL);	
	  }	

	return bRetVal;
}
//*****************************************************************************
//
//function:Config Microphone Boost function
//
//*****************************************************************************
BOOL RT_CodecComm::ConfigMicBoost(BYTE Mic,MIC_BOOST_TYPE BoostType)
{
	BOOL bRetVal=FALSE;

	if(Mic==MIC1)
	{
		switch(BoostType)
		{
			//Bypass mic1 boost
			case BOOST_BYPASS:

				bRetVal=WriteCodecRegMask(RT_MICROPHONE_CTRL,MIC1_BOOST_CONTROL_BYPASS,MIC1_BOOST_CONTROL_MASK);

			break;
			//Set mic1 boost to 20DB	
			case BOOST_20DB:

				bRetVal=WriteCodecRegMask(RT_MICROPHONE_CTRL,MIC1_BOOST_CONTROL_20DB,MIC1_BOOST_CONTROL_MASK);

			break;
			//Set mic1 boost to 30DB
			case BOOST_30DB:

				bRetVal=WriteCodecRegMask(RT_MICROPHONE_CTRL,MIC1_BOOST_CONTROL_30DB,MIC1_BOOST_CONTROL_MASK);

			break;
			//Set mic1 boost to 40DB
			case BOOST_40DB:

				bRetVal=WriteCodecRegMask(RT_MICROPHONE_CTRL,MIC1_BOOST_CONTROL_40DB,MIC1_BOOST_CONTROL_MASK);	

			break;

			default:
				bRetVal=FALSE;
				
		}
	}
	else if(Mic==MIC2)
	{
		switch(BoostType)
		{
			//Bypass mic2 boost
			case BOOST_BYPASS:

				bRetVal=WriteCodecRegMask(RT_MICROPHONE_CTRL,MIC2_BOOST_CONTROL_BYPASS,MIC2_BOOST_CONTROL_MASK);

			break;
			//Set mic2 boost to 20DB
			case BOOST_20DB:

				bRetVal=WriteCodecRegMask(RT_MICROPHONE_CTRL,MIC2_BOOST_CONTROL_20DB,MIC2_BOOST_CONTROL_MASK);

			break;
			//Set mic2 boost to 30DB
			case BOOST_30DB:

				bRetVal=WriteCodecRegMask(RT_MICROPHONE_CTRL,MIC2_BOOST_CONTROL_30DB,MIC2_BOOST_CONTROL_MASK);

			break;
			//Set mic2 boost to 40DB
			case BOOST_40DB:

				bRetVal=WriteCodecRegMask(RT_MICROPHONE_CTRL,MIC2_BOOST_CONTROL_40DB,MIC2_BOOST_CONTROL_MASK);