📄 gen_4psk.mdl
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Model {
Name "gen_4psk"
Version 5.0
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Mon Jul 07 16:49:48 2003"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "tt"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Wed Dec 14 21:54:02 2005"
ModelVersionFormat "1.%<AutoIncrement:62>"
ConfigurationManager "None"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "ode45"
SolverMode "Auto"
StartTime "0.0"
StopTime "10.0"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType on
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType ComplexToRealImag
Output "Real and imag"
}
Block {
BlockType Constant
Value "1"
VectorParams1D on
ShowAdditionalParam off
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
}
Block {
BlockType DataTypeConversion
DataType "auto"
SaturateOnIntegerOverflow on
}
Block {
BlockType Inport
Port "1"
PortDimensions "-1"
SampleTime "-1"
ShowAdditionalParam off
LatchInput off
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
Interpolate on
}
Block {
BlockType Math
Operator "exp"
OutputSignalType "auto"
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
}
Block {
BlockType Outport
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType Reference
}
Block {
BlockType Rounding
Operator "floor"
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType ToWorkspace
VariableName "simulink_output"
MaxDataPoints "1000"
Decimation "1"
SampleTime "0"
}
Block {
BlockType ZeroOrderHold
SampleTime "1"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "gen_4psk"
Location [2, 86, 1014, 736]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "4-PSK\nModulator\nBaseband"
Ports [1, 1]
Position [115, 74, 190, 126]
SourceBlock "commdigbbndpm2/M-PSK\nModulator\nBaseband"
SourceType "M-PSK Modulator Baseband"
M "4"
InType "Integer"
Enc "Binary"
Ph "pi/4"
numSamp "1"
}
Block {
BlockType ComplexToRealImag
Name "Complex to\nReal-Imag"
Ports [1, 2]
Position [320, 82, 350, 113]
Output "Real and imag"
}
Block {
BlockType Reference
Name "DSB AM\nModulator\nPassband"
Ports [1, 1]
Position [380, 37, 455, 83]
SourceBlock "commanapbnd2/DSB AM\nModulator\nPassband"
SourceType "DSB AM Modulator Passband"
Offset "0"
Fc "4800"
Ph "0"
}
Block {
BlockType Reference
Name "DSB AM\nModulator\nPassband1"
Ports [1, 1]
Position [380, 137, 455, 183]
SourceBlock "commanapbnd2/DSB AM\nModulator\nPassband"
SourceType "DSB AM Modulator Passband"
Offset "0"
Fc "4800"
Ph "pi/2"
}
Block {
BlockType Reference
Name "FIR\nInterpolation"
Ports [1, 1]
Position [215, 74, 280, 126]
SourceBlock "dspmlti3/FIR\nInterpolation"
SourceType "FIR Interpolation"
h "rcosine(1,16,'normal',0.3)"
L "16"
framing "Maintain input frame size"
outputBufInitCond "0"
}
Block {
BlockType Reference
Name "Random Integer\nGenerator"
Ports [0, 1]
Position [15, 78, 95, 122]
FontName "Arial"
SourceBlock "commrandsrc2/Random Integer\nGenerator"
SourceType "Random Integer Generator"
mul "4"
seed "37"
Ts "1/1200"
frameBased off
sampPerFrame "1"
orient off
}
Block {
BlockType Reference
Name "Spectrum\nScope"
Ports [1]
Position [615, 225, 650, 275]
SourceBlock "dspsnks4/Spectrum\nScope"
SourceType "Spectrum Scope"
ScopeProperties off
Domain "Frequency"
HorizSpan "1"
UseBuffer on
BufferSize "512"
Overlap "256"
inpFftLenInherit on
FFTlength "512"
numAvg "20"
DisplayProperties off
AxisGrid on
Memory off
FrameNumber on
AxisLegend off
AxisZoom off
OpenScopeAtSimStart on
OpenScopeImmediately off
FigPos "get(0,'defaultfigureposition')"
AxisProperties on
XUnits "Hertz"
XRange "[0...Fs/2]"
InheritXIncr on
XIncr "1.0"
XLabel "Samples"
YUnits "dB"
YMin "-80"
YMax "30"
YLabel "Magnitude, dB"
LineProperties off
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [490, 85, 510, 105]
ShowName off
IconShape "round"
Inputs "|++"
ShowAdditionalParam on
InputSameDT off
}
Block {
BlockType ToWorkspace
Name "To Workspace"
Position [615, 80, 675, 110]
VariableName "gen_signal"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType ZeroOrderHold
Name "Zero-Order\nHold"
Position [540, 76, 575, 114]
SampleTime "1/60000"
}
Line {
SrcBlock "FIR\nInterpolation"
SrcPort 1
DstBlock "Complex to\nReal-Imag"
DstPort 1
}
Line {
SrcBlock "Random Integer\nGenerator"
SrcPort 1
DstBlock "4-PSK\nModulator\nBaseband"
DstPort 1
}
Line {
SrcBlock "4-PSK\nModulator\nBaseband"
SrcPort 1
DstBlock "FIR\nInterpolation"
DstPort 1
}
Line {
SrcBlock "Complex to\nReal-Imag"
SrcPort 1
Points [5, 0; 0, -30]
DstBlock "DSB AM\nModulator\nPassband"
DstPort 1
}
Line {
SrcBlock "Complex to\nReal-Imag"
SrcPort 2
Points [10, 0]
DstBlock "DSB AM\nModulator\nPassband1"
DstPort 1
}
Line {
SrcBlock "DSB AM\nModulator\nPassband"
SrcPort 1
Points [5, 0; 0, 35]
DstBlock "Sum"
DstPort 1
}
Line {
SrcBlock "DSB AM\nModulator\nPassband1"
SrcPort 1
Points [40, 0]
DstBlock "Sum"
DstPort 2
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "Zero-Order\nHold"
DstPort 1
}
Line {
SrcBlock "Zero-Order\nHold"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "To Workspace"
DstPort 1
}
Branch {
Points [0, 155]
DstBlock "Spectrum\nScope"
DstPort 1
}
}
}
}
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