dds.map.qmsg

基于DD的数字移相正弦信号发生器设计 EDA技术在全国大学生设计竞赛中的应用

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 17 21:53:18 2008 " "Info: Processing started: Tue Jun 17 21:53:18 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dds -c dds " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SUM99.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SUM99.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SUM99-ART " "Info: Found design unit 1: SUM99-ART" {  } { { "SUM99.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/SUM99.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SUM99 " "Info: Found entity 1: SUM99" {  } { { "SUM99.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/SUM99.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDS.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DDS.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DDS-ART " "Info: Found design unit 1: DDS-ART" {  } { { "DDS.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/DDS.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DDS " "Info: Found entity 1: DDS" {  } { { "DDS.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/DDS.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG1-ART " "Info: Found design unit 1: REG1-ART" {  } { { "REG1.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/REG1.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG1 " "Info: Found entity 1: REG1" {  } { { "REG1.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/REG1.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG2-ART " "Info: Found design unit 1: REG2-ART" {  } { { "REG2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/REG2.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG2 " "Info: Found entity 1: REG2" {  } { { "REG2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/REG2.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ROM.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ROM.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ROM-ART " "Info: Found design unit 1: ROM-ART" {  } { { "ROM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/ROM.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Info: Found entity 1: ROM" {  } { { "ROM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/ROM.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dds " "Info: Elaborating entity \"dds\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SUM99 SUM99:U0 " "Info: Elaborating entity \"SUM99\" for hierarchy \"SUM99:U0\"" {  } { { "DDS.vhd" "U0" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/DDS.vhd" 39 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "TEMP SUM99.vhd(26) " "Warning (10492): VHDL Process Statement warning at SUM99.vhd(26): signal \"TEMP\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "SUM99.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/SUM99.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG1 REG1:U1 " "Info: Elaborating entity \"REG1\" for hierarchy \"REG1:U1\"" {  } { { "DDS.vhd" "U1" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/DDS.vhd" 40 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:U2 " "Info: Elaborating entity \"ROM\" for hierarchy \"ROM:U2\"" {  } { { "DDS.vhd" "U2" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/DDS.vhd" 41 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG2 REG2:U3 " "Info: Elaborating entity \"REG2\" for hierarchy \"REG2:U3\"" {  } { { "DDS.vhd" "U3" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/DDS.vhd" 42 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "SUM99:U0\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"SUM99:U0\|lpm_add_sub:Add0\"" {  } { { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus60/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}