dds.tan.qmsg

基于DD的数字移相正弦信号发生器设计 EDA技术在全国大学生设计竞赛中的应用

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "DDS.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/DDS.vhd" 9 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register REG1:U1\|Q\[6\] register ROM:U2\|OUTP\[0\] 48.78 MHz 20.5 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 48.78 MHz between source register \"REG1:U1\|Q\[6\]\" and destination register \"ROM:U2\|OUTP\[0\]\" (period= 20.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.700 ns + Longest register register " "Info: + Longest register to register delay is 18.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG1:U1\|Q\[6\] 1 REG LC2_J10 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_J10; Fanout = 2; REG Node = 'REG1:U1\|Q\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { REG1:U1|Q[6] } "NODE_NAME" } } { "REG1.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/REG1.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 3.100 ns ROM:U2\|Equal0~72 2 COMB LC8_J8 2 " "Info: 2: + IC(1.100 ns) + CELL(2.000 ns) = 3.100 ns; Loc. = LC8_J8; Fanout = 2; COMB Node = 'ROM:U2\|Equal0~72'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { REG1:U1|Q[6] ROM:U2|Equal0~72 } "NODE_NAME" } } { "ROM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/ROM.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 5.000 ns ROM:U2\|Equal0~75 3 COMB LC1_J8 3 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 5.000 ns; Loc. = LC1_J8; Fanout = 3; COMB Node = 'ROM:U2\|Equal0~75'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { ROM:U2|Equal0~72 ROM:U2|Equal0~75 } "NODE_NAME" } } { "ROM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/ROM.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.900 ns) 8.000 ns ROM:U2\|Equal1~50 4 COMB LC5_J5 4 " "Info: 4: + IC(1.100 ns) + CELL(1.900 ns) = 8.000 ns; Loc. = LC5_J5; Fanout = 4; COMB Node = 'ROM:U2\|Equal1~50'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { ROM:U2|Equal0~75 ROM:U2|Equal1~50 } "NODE_NAME" } } { "ROM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/ROM.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 9.900 ns ROM:U2\|Equal3~52 5 COMB LC2_J5 2 " "Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 9.900 ns; Loc. = LC2_J5; Fanout = 2; COMB Node = 'ROM:U2\|Equal3~52'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { ROM:U2|Equal1~50 ROM:U2|Equal3~52 } "NODE_NAME" } } { "ROM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/ROM.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.200 ns) 12.300 ns ROM:U2\|WideOr4~96 6 COMB LC1_J5 1 " "Info: 6: + IC(0.200 ns) + CELL(2.200 ns) = 12.300 ns; Loc. = LC1_J5; Fanout = 1; COMB Node = 'ROM:U2\|WideOr4~96'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { ROM:U2|Equal3~52 ROM:U2|WideOr4~96 } "NODE_NAME" } } { "ROM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/ROM.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.700 ns) 15.000 ns ROM:U2\|WideOr4~97 7 COMB LC1_J2 2 " "Info: 7: + IC(1.000 ns) + CELL(1.700 ns) = 15.000 ns; Loc. = LC1_J2; Fanout = 2; COMB Node = 'ROM:U2\|WideOr4~97'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { ROM:U2|WideOr4~96 ROM:U2|WideOr4~97 } "NODE_NAME" } } { "ROM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/ROM.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 17.200 ns ROM:U2\|WideOr6~75 8 COMB LC4_J2 1 " "Info: 8: + IC(0.200 ns) + CELL(2.000 ns) = 17.200 ns; Loc. = LC4_J2; Fanout = 1; COMB Node = 'ROM:U2\|WideOr6~75'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.200 ns" { ROM:U2|WideOr4~97 ROM:U2|WideOr6~75 } "NODE_NAME" } } { "ROM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/ROM.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.300 ns) 18.700 ns ROM:U2\|OUTP\[0\] 9 REG LC3_J2 1 " "Info: 9: + IC(0.200 ns) + CELL(1.300 ns) = 18.700 ns; Loc. = LC3_J2; Fanout = 1; REG Node = 'ROM:U2\|OUTP\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { ROM:U2|WideOr6~75 ROM:U2|OUTP[0] } "NODE_NAME" } } { "ROM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/ROM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.500 ns ( 77.54 % ) " "Info: Total cell delay = 14.500 ns ( 77.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns ( 22.46 % ) " "Info: Total interconnect delay = 4.200 ns ( 22.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "18.700 ns" { REG1:U1|Q[6] ROM:U2|Equal0~72 ROM:U2|Equal0~75 ROM:U2|Equal1~50 ROM:U2|Equal3~52 ROM:U2|WideOr4~96 ROM:U2|WideOr4~97 ROM:U2|WideOr6~75 ROM:U2|OUTP[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "18.700 ns" { REG1:U1|Q[6] ROM:U2|Equal0~72 ROM:U2|Equal0~75 ROM:U2|Equal1~50 ROM:U2|Equal3~52 ROM:U2|WideOr4~96 ROM:U2|WideOr4~97 ROM:U2|WideOr6~75 ROM:U2|OUTP[0] } { 0.000ns 1.100ns 0.200ns 1.100ns 0.200ns 0.200ns 1.000ns 0.200ns 0.200ns } { 0.000ns 2.000ns 1.700ns 1.900ns 1.700ns 2.200ns 1.700ns 2.000ns 1.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 36 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 36; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/DDS.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns ROM:U2\|OUTP\[0\] 2 REG LC3_J2 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_J2; Fanout = 1; REG Node = 'ROM:U2\|OUTP\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK ROM:U2|OUTP[0] } "NODE_NAME" } } { "ROM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/ROM.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK ROM:U2|OUTP[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out ROM:U2|OUTP[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 36 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 36; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/DDS.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns REG1:U1\|Q\[6\] 2 REG LC2_J10 2 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_J10; Fanout = 2; REG Node = 'REG1:U1\|Q\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK REG1:U1|Q[6] } "NODE_NAME" } } { "REG1.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/REG1.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK REG1:U1|Q[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out REG1:U1|Q[6] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK ROM:U2|OUTP[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out ROM:U2|OUTP[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK REG1:U1|Q[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out REG1:U1|Q[6] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "REG1.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/REG1.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "ROM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/ROM.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "18.700 ns" { REG1:U1|Q[6] ROM:U2|Equal0~72 ROM:U2|Equal0~75 ROM:U2|Equal1~50 ROM:U2|Equal3~52 ROM:U2|WideOr4~96 ROM:U2|WideOr4~97 ROM:U2|WideOr6~75 ROM:U2|OUTP[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "18.700 ns" { REG1:U1|Q[6] ROM:U2|Equal0~72 ROM:U2|Equal0~75 ROM:U2|Equal1~50 ROM:U2|Equal3~52 ROM:U2|WideOr4~96 ROM:U2|WideOr4~97 ROM:U2|WideOr6~75 ROM:U2|OUTP[0] } { 0.000ns 1.100ns 0.200ns 1.100ns 0.200ns 0.200ns 1.000ns 0.200ns 0.200ns } { 0.000ns 2.000ns 1.700ns 1.900ns 1.700ns 2.200ns 1.700ns 2.000ns 1.300ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK ROM:U2|OUTP[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out ROM:U2|OUTP[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK REG1:U1|Q[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out REG1:U1|Q[6] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "SUM99:U0\|TEMP\[6\] K\[1\] CLK 13.600 ns register " "Info: tsu for register \"SUM99:U0\|TEMP\[6\]\" (data pin = \"K\[1\]\", clock pin = \"CLK\") is 13.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.800 ns + Longest pin register " "Info: + Longest pin to register delay is 14.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns K\[1\] 1 PIN PIN_203 2 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_203; Fanout = 2; PIN Node = 'K\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { K[1] } "NODE_NAME" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/DDS.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(0.700 ns) 8.500 ns SUM99:U0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 2 COMB LC5_J30 2 " "Info: 2: + IC(4.700 ns) + CELL(0.700 ns) = 8.500 ns; Loc. = LC5_J30; Fanout = 2; COMB Node = 'SUM99:U0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { K[1] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.700 ns SUM99:U0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 3 COMB LC6_J30 2 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 8.700 ns; Loc. = LC6_J30; Fanout = 2; COMB Node = 'SUM99:U0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.900 ns SUM99:U0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 4 COMB LC7_J30 2 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 8.900 ns; Loc. = LC7_J30; Fanout = 2; COMB Node = 'SUM99:U0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 9.100 ns SUM99:U0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 5 COMB LC8_J30 2 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 9.100 ns; Loc. = LC8_J30; Fanout = 2; COMB Node = 'SUM99:U0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.200 ns) 10.200 ns SUM99:U0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 6 COMB LC1_J32 2 " "Info: 6: + IC(0.900 ns) + CELL(0.200 ns) = 10.200 ns; Loc. = LC1_J32; Fanout = 2; COMB Node = 'SUM99:U0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.100 ns" { SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 11.800 ns SUM99:U0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[6\] 7 COMB LC2_J32 1 " "Info: 7: + IC(0.000 ns) + CELL(1.600 ns) = 11.800 ns; Loc. = LC2_J32; Fanout = 1; COMB Node = 'SUM99:U0\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.000 ns) 14.800 ns SUM99:U0\|TEMP\[6\] 8 REG LC6_J10 3 " "Info: 8: + IC(2.000 ns) + CELL(1.000 ns) = 14.800 ns; Loc. = LC6_J10; Fanout = 3; REG Node = 'SUM99:U0\|TEMP\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] SUM99:U0|TEMP[6] } "NODE_NAME" } } { "SUM99.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/SUM99.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 48.65 % ) " "Info: Total cell delay = 7.200 ns ( 48.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.600 ns ( 51.35 % ) " "Info: Total interconnect delay = 7.600 ns ( 51.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.800 ns" { K[1] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] SUM99:U0|TEMP[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.800 ns" { K[1] K[1]~out SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] SUM99:U0|TEMP[6] } { 0.000ns 0.000ns 4.700ns 0.000ns 0.000ns 0.000ns 0.900ns 0.000ns 2.000ns } { 0.000ns 3.100ns 0.700ns 0.200ns 0.200ns 0.200ns 0.200ns 1.600ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "SUM99.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/SUM99.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_79 36 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 36; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/DDS.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns SUM99:U0\|TEMP\[6\] 2 REG LC6_J10 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC6_J10; Fanout = 3; REG Node = 'SUM99:U0\|TEMP\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK SUM99:U0|TEMP[6] } "NODE_NAME" } } { "SUM99.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS做/SUM99.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK SUM99:U0|TEMP[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out SUM99:U0|TEMP[6] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.800 ns" { K[1] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] SUM99:U0|TEMP[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.800 ns" { K[1] K[1]~out SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] SUM99:U0|TEMP[6] } { 0.000ns 0.000ns 4.700ns 0.000ns 0.000ns 0.000ns 0.900ns 0.000ns 2.000ns } { 0.000ns 3.100ns 0.700ns 0.200ns 0.200ns 0.200ns 0.200ns 1.600ns 1.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK SUM99:U0|TEMP[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out SUM99:U0|TEMP[6] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}