dds.tan.rpt

基于DD的数字移相正弦信号发生器设计 EDA技术在全国大学生设计竞赛中的应用

; N/A           ; None        ; -7.200 ns  ; K[5] ; SUM99:U0|TEMP[8] ; CLK      ;
; N/A           ; None        ; -7.400 ns  ; K[5] ; SUM99:U0|TEMP[9] ; CLK      ;
; N/A           ; None        ; -7.500 ns  ; K[6] ; SUM99:U0|TEMP[6] ; CLK      ;
; N/A           ; None        ; -8.000 ns  ; K[8] ; SUM99:U0|TEMP[8] ; CLK      ;
; N/A           ; None        ; -8.100 ns  ; K[7] ; SUM99:U0|TEMP[7] ; CLK      ;
; N/A           ; None        ; -8.100 ns  ; K[4] ; SUM99:U0|TEMP[4] ; CLK      ;
; N/A           ; None        ; -8.300 ns  ; K[8] ; SUM99:U0|TEMP[9] ; CLK      ;
; N/A           ; None        ; -8.300 ns  ; K[5] ; SUM99:U0|TEMP[5] ; CLK      ;
; N/A           ; None        ; -8.400 ns  ; K[7] ; SUM99:U0|TEMP[8] ; CLK      ;
; N/A           ; None        ; -8.500 ns  ; K[2] ; SUM99:U0|TEMP[3] ; CLK      ;
; N/A           ; None        ; -8.600 ns  ; K[7] ; SUM99:U0|TEMP[9] ; CLK      ;
; N/A           ; None        ; -8.600 ns  ; K[5] ; SUM99:U0|TEMP[6] ; CLK      ;
; N/A           ; None        ; -8.700 ns  ; K[1] ; SUM99:U0|TEMP[3] ; CLK      ;
; N/A           ; None        ; -8.700 ns  ; K[2] ; SUM99:U0|TEMP[4] ; CLK      ;
; N/A           ; None        ; -8.900 ns  ; K[1] ; SUM99:U0|TEMP[4] ; CLK      ;
; N/A           ; None        ; -9.200 ns  ; K[1] ; SUM99:U0|TEMP[1] ; CLK      ;
; N/A           ; None        ; -9.200 ns  ; K[2] ; SUM99:U0|TEMP[2] ; CLK      ;
; N/A           ; None        ; -9.500 ns  ; K[1] ; SUM99:U0|TEMP[2] ; CLK      ;
; N/A           ; None        ; -9.700 ns  ; K[4] ; SUM99:U0|TEMP[7] ; CLK      ;
; N/A           ; None        ; -9.900 ns  ; K[4] ; SUM99:U0|TEMP[8] ; CLK      ;
; N/A           ; None        ; -10.100 ns ; K[4] ; SUM99:U0|TEMP[9] ; CLK      ;
; N/A           ; None        ; -10.200 ns ; K[2] ; SUM99:U0|TEMP[7] ; CLK      ;
; N/A           ; None        ; -10.400 ns ; K[1] ; SUM99:U0|TEMP[7] ; CLK      ;
; N/A           ; None        ; -10.400 ns ; K[2] ; SUM99:U0|TEMP[8] ; CLK      ;
; N/A           ; None        ; -10.600 ns ; K[1] ; SUM99:U0|TEMP[8] ; CLK      ;
; N/A           ; None        ; -10.600 ns ; K[2] ; SUM99:U0|TEMP[9] ; CLK      ;
; N/A           ; None        ; -10.800 ns ; K[1] ; SUM99:U0|TEMP[9] ; CLK      ;
; N/A           ; None        ; -11.100 ns ; K[4] ; SUM99:U0|TEMP[5] ; CLK      ;
; N/A           ; None        ; -11.300 ns ; K[4] ; SUM99:U0|TEMP[6] ; CLK      ;
; N/A           ; None        ; -11.600 ns ; K[2] ; SUM99:U0|TEMP[5] ; CLK      ;
; N/A           ; None        ; -11.800 ns ; K[1] ; SUM99:U0|TEMP[5] ; CLK      ;
; N/A           ; None        ; -11.800 ns ; K[2] ; SUM99:U0|TEMP[6] ; CLK      ;
; N/A           ; None        ; -12.000 ns ; K[1] ; SUM99:U0|TEMP[6] ; CLK      ;
+---------------+-------------+------------+------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Jun 17 21:54:14 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dds -c dds
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 48.78 MHz between source register "REG1:U1|Q[6]" and destination register "ROM:U2|OUTP[0]" (period= 20.5 ns)
    Info: + Longest register to register delay is 18.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_J10; Fanout = 2; REG Node = 'REG1:U1|Q[6]'
        Info: 2: + IC(1.100 ns) + CELL(2.000 ns) = 3.100 ns; Loc. = LC8_J8; Fanout = 2; COMB Node = 'ROM:U2|Equal0~72'
        Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 5.000 ns; Loc. = LC1_J8; Fanout = 3; COMB Node = 'ROM:U2|Equal0~75'
        Info: 4: + IC(1.100 ns) + CELL(1.900 ns) = 8.000 ns; Loc. = LC5_J5; Fanout = 4; COMB Node = 'ROM:U2|Equal1~50'
        Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 9.900 ns; Loc. = LC2_J5; Fanout = 2; COMB Node = 'ROM:U2|Equal3~52'
        Info: 6: + IC(0.200 ns) + CELL(2.200 ns) = 12.300 ns; Loc. = LC1_J5; Fanout = 1; COMB Node = 'ROM:U2|WideOr4~96'
        Info: 7: + IC(1.000 ns) + CELL(1.700 ns) = 15.000 ns; Loc. = LC1_J2; Fanout = 2; COMB Node = 'ROM:U2|WideOr4~97'
        Info: 8: + IC(0.200 ns) + CELL(2.000 ns) = 17.200 ns; Loc. = LC4_J2; Fanout = 1; COMB Node = 'ROM:U2|WideOr6~75'
        Info: 9: + IC(0.200 ns) + CELL(1.300 ns) = 18.700 ns; Loc. = LC3_J2; Fanout = 1; REG Node = 'ROM:U2|OUTP[0]'
        Info: Total cell delay = 14.500 ns ( 77.54 % )
        Info: Total interconnect delay = 4.200 ns ( 22.46 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 36; CLK Node = 'CLK'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_J2; Fanout = 1; REG Node = 'ROM:U2|OUTP[0]'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
        Info: - Longest clock path from clock "CLK" to source register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 36; CLK Node = 'CLK'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_J10; Fanout = 2; REG Node = 'REG1:U1|Q[6]'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 0.700 ns
Info: tsu for register "SUM99:U0|TEMP[6]" (data pin = "K[1]", clock pin = "CLK") is 13.600 ns
    Info: + Longest pin to register delay is 14.800 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_203; Fanout = 2; PIN Node = 'K[1]'
        Info: 2: + IC(4.700 ns) + CELL(0.700 ns) = 8.500 ns; Loc. = LC5_J30; Fanout = 2; COMB Node = 'SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]'
        Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 8.700 ns; Loc. = LC6_J30; Fanout = 2; COMB Node = 'SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2]'
        Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 8.900 ns; Loc. = LC7_J30; Fanout = 2; COMB Node = 'SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3]'
        Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 9.100 ns; Loc. = LC8_J30; Fanout = 2; COMB Node = 'SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4]'
        Info: 6: + IC(0.900 ns) + CELL(0.200 ns) = 10.200 ns; Loc. = LC1_J32; Fanout = 2; COMB Node = 'SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5]'
        Info: 7: + IC(0.000 ns) + CELL(1.600 ns) = 11.800 ns; Loc. = LC2_J32; Fanout = 1; COMB Node = 'SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]'
        Info: 8: + IC(2.000 ns) + CELL(1.000 ns) = 14.800 ns; Loc. = LC6_J10; Fanout = 3; REG Node = 'SUM99:U0|TEMP[6]'
        Info: Total cell delay = 7.200 ns ( 48.65 % )
        Info: Total interconnect delay = 7.600 ns ( 51.35 % )
    Info: + Micro setup delay of destination is 0.700 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 36; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC6_J10; Fanout = 3; REG Node = 'SUM99:U0|TEMP[6]'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: tco from clock "CLK" to destination pin "Q[5]" through register "REG2:U3|Q[5]" is 14.700 ns
    Info: + Longest clock path from clock "CLK" to source register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 36; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_J3; Fanout = 1; REG Node = 'REG2:U3|Q[5]'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 11.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_J3; Fanout = 1; REG Node = 'REG2:U3|Q[5]'
        Info: 2: + IC(3.100 ns) + CELL(8.600 ns) = 11.700 ns; Loc. = PIN_150; Fanout = 0; PIN Node = 'Q[5]'
        Info: Total cell delay = 8.600 ns ( 73.50 % )
        Info: Total interconnect delay = 3.100 ns ( 26.50 % )
Info: th for register "SUM99:U0|TEMP[5]" (data pin = "EN", clock pin = "CLK") is 0.500 ns
    Info: + Longest clock path from clock "CLK" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 36; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_J10; Fanout = 3; REG Node = 'SUM99:U0|TEMP[5]'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro hold delay of destination is 0.900 ns
    Info: - Shortest pin to register delay is 2.300 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 10; PIN Node = 'EN'
        Info: 2: + IC(1.500 ns) + CELL(0.300 ns) = 2.300 ns; Loc. = LC5_J10; Fanout = 3; REG Node = 'SUM99:U0|TEMP[5]'
        Info: Total cell delay = 0.800 ns ( 34.78 % )
        Info: Total interconnect delay = 1.500 ns ( 65.22 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Jun 17 21:54:17 2008
    Info: Elapsed time: 00:00:04