dds.tan.summary

基于DD的数字移相正弦信号发生器设计 EDA技术在全国大学生设计竞赛中的应用

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 13.600 ns
From           : K[1]
To             : SUM99:U0|TEMP[6]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.700 ns
From           : REG2:U3|Q[5]
To             : Q[5]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.500 ns
From           : EN
To             : SUM99:U0|TEMP[6]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 48.78 MHz ( period = 20.500 ns )
From           : REG1:U1|Q[6]
To             : ROM:U2|OUTP[0]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------