rom.vhd

基于DD的数字移相正弦信号发生器设计 EDA技术在全国大学生设计竞赛中的应用

--ROM.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ROM IS
  PORT(ADDR: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
       CLK: IN STD_LOGIC;
       OUTP: OUT SIGNED(8 DOWNTO 0));
END ENTITY ROM;
ARCHITECTURE ART OF ROM IS
BEGIN
PROCESS (CLK) IS
BEGIN
IF (CLK'EVENT AND CLK='1')THEN
CASE ADDR IS
WHEN "0000000000"=>OUTP<="000000000";
WHEN "0000000001"=>OUTP<="000000010";
WHEN "0000000010"=>OUTP<="000000011";
WHEN "0000000011"=>OUTP<="000000101";
WHEN "0000000100"=>OUTP<="000000110";
WHEN "0000000101"=>OUTP<="000001000";
WHEN "0000000110"=>OUTP<="000001001";
WHEN "0000000111"=>OUTP<="000001011";
WHEN "0000001000"=>OUTP<="000001101";
WHEN "0000001001"=>OUTP<="000001110";
WHEN "0000001010"=>OUTP<="000010000";
WHEN "1111101001"=>OUTP<="111011100";
WHEN "1111101010"=>OUTP<="111011110";
WHEN "1111101011"=>OUTP<="111011111";
WHEN "1111101100"=>OUTP<="111100001";
WHEN "1111101101"=>OUTP<="111100010";
WHEN "1111101110"=>OUTP<="111100100";
WHEN "1111101111"=>OUTP<="111100101";
WHEN "1111110000"=>OUTP<="111100111";
WHEN "1111110001"=>OUTP<="111101001";
WHEN "1111110010"=>OUTP<="111101010";
WHEN "1111110011"=>OUTP<="111101100";
WHEN "1111110100"=>OUTP<="111101101";
WHEN "1111110101"=>OUTP<="111101111";
WHEN "1111110110"=>OUTP<="111110000";
WHEN "1111110111"=>OUTP<="111110010";
WHEN "1111111000"=>OUTP<="111110011";
WHEN "1111111001"=>OUTP<="111110101";
WHEN "1111111010"=>OUTP<="111110111";
WHEN "1111111011"=>OUTP<="111111010";
WHEN "1111111100"=>OUTP<="111111011";
WHEN "1111111101"=>OUTP<="111111101";
WHEN "1111111110"=>OUTP<="111111110";
WHEN "1111111111"=>OUTP<="000000000";
WHEN OTHERS=>OUTP<="000000000";
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE ART;