📄 dds.map.rpt
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+-----------------------------------+---------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------+
; |DDS ; 101 (0) ; 34 ; 0 ; 22 ; 67 (0) ; 27 (0) ; 7 (0) ; 10 (0) ; 0 (0) ; |DDS ;
; |REG1:U1| ; 10 (10) ; 10 ; 0 ; 0 ; 0 (0) ; 10 (10) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS|REG1:U1 ;
; |REG2:U3| ; 7 (7) ; 7 ; 0 ; 0 ; 0 (0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS|REG2:U3 ;
; |ROM:U2| ; 64 (64) ; 7 ; 0 ; 0 ; 57 (57) ; 0 (0) ; 7 (7) ; 0 (0) ; 0 (0) ; |DDS|ROM:U2 ;
; |SUM99:U0| ; 20 (10) ; 10 ; 0 ; 0 ; 10 (0) ; 10 (10) ; 0 (0) ; 10 (0) ; 0 (0) ; |DDS|SUM99:U0 ;
; |lpm_add_sub:Add0| ; 10 (0) ; 0 ; 0 ; 0 ; 10 (0) ; 0 (0) ; 0 (0) ; 10 (0) ; 0 (0) ; |DDS|SUM99:U0|lpm_add_sub:Add0 ;
; |addcore:adder| ; 10 (1) ; 0 ; 0 ; 0 ; 10 (1) ; 0 (0) ; 0 (0) ; 10 (1) ; 0 (0) ; |DDS|SUM99:U0|lpm_add_sub:Add0|addcore:adder ;
; |a_csnbuffer:result_node| ; 9 (9) ; 0 ; 0 ; 0 ; 9 (9) ; 0 (0) ; 0 (0) ; 9 (9) ; 0 (0) ; |DDS|SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 34 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 10 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 10 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: SUM99:U0|lpm_add_sub:Add0 ;
+------------------------+-------------+-------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+-------------------------------------+
; LPM_WIDTH ; 10 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_djh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Jun 17 21:53:18 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds
Info: Found 2 design units, including 1 entities, in source file SUM99.vhd
Info: Found design unit 1: SUM99-ART
Info: Found entity 1: SUM99
Info: Found 2 design units, including 1 entities, in source file DDS.vhd
Info: Found design unit 1: DDS-ART
Info: Found entity 1: DDS
Info: Found 2 design units, including 1 entities, in source file REG1.vhd
Info: Found design unit 1: REG1-ART
Info: Found entity 1: REG1
Info: Found 2 design units, including 1 entities, in source file REG2.vhd
Info: Found design unit 1: REG2-ART
Info: Found entity 1: REG2
Info: Found 2 design units, including 1 entities, in source file ROM.vhd
Info: Found design unit 1: ROM-ART
Info: Found entity 1: ROM
Info: Elaborating entity "dds" for the top level hierarchy
Info: Elaborating entity "SUM99" for hierarchy "SUM99:U0"
Warning (10492): VHDL Process Statement warning at SUM99.vhd(26): signal "TEMP" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "REG1" for hierarchy "REG1:U1"
Info: Elaborating entity "ROM" for hierarchy "ROM:U2"
Info: Elaborating entity "REG2" for hierarchy "REG2:U3"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "SUM99:U0|lpm_add_sub:Add0"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Elaborated megafunction instantiation "SUM99:U0|lpm_add_sub:Add0|addcore:adder", which is child of megafunction instantiation "SUM99:U0|lpm_add_sub:Add0"
Info: Instantiated megafunction "SUM99:U0|lpm_add_sub:Add0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "10"
Info: Parameter "LPM_DIRECTION" = "ADD"
Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Elaborated megafunction instantiation "SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "SUM99:U0|lpm_add_sub:Add0"
Info: Instantiated megafunction "SUM99:U0|lpm_add_sub:Add0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "10"
Info: Parameter "LPM_DIRECTION" = "ADD"
Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Elaborated megafunction instantiation "SUM99:U0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "SUM99:U0|lpm_add_sub:Add0"
Info: Instantiated megafunction "SUM99:U0|lpm_add_sub:Add0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "10"
Info: Parameter "LPM_DIRECTION" = "ADD"
Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Elaborated megafunction instantiation "SUM99:U0|lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "SUM99:U0|lpm_add_sub:Add0"
Info: Instantiated megafunction "SUM99:U0|lpm_add_sub:Add0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "10"
Info: Parameter "LPM_DIRECTION" = "ADD"
Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Elaborated megafunction instantiation "SUM99:U0|lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "SUM99:U0|lpm_add_sub:Add0"
Info: Instantiated megafunction "SUM99:U0|lpm_add_sub:Add0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "10"
Info: Parameter "LPM_DIRECTION" = "ADD"
Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Duplicate registers merged to single register
Info: Duplicate register "ROM:U2|OUTP[8]" merged to single register "ROM:U2|OUTP[6]"
Info: Duplicate register "ROM:U2|OUTP[7]" merged to single register "ROM:U2|OUTP[6]"
Info: Duplicate register "REG2:U3|Q[8]" merged to single register "REG2:U3|Q[6]"
Info: Duplicate register "REG2:U3|Q[7]" merged to single register "REG2:U3|Q[6]"
Info: Implemented 123 device resources after synthesis - the final resource count might be different
Info: Implemented 13 input pins
Info: Implemented 9 output pins
Info: Implemented 101 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Processing ended: Tue Jun 17 21:53:27 2008
Info: Elapsed time: 00:00:09
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