apiex.h

这是一个单片机开发程序

#pragma once

#include <windows.h>

/*
 *	Prototype for Interrupt Service Routine
 */

typedef void (*ISR_ROUTINE)();
typedef void (*DMAFSR_ROUTINE)();


/*
 *	Interface Routines
 */

BOOL Startup();
void Cleanup();

BOOL PortReadByte(DWORD address, BYTE *pdata);
BOOL PortWriteByte(DWORD address, BYTE data);
BOOL MemReadByte(DWORD address, BYTE *pdata);
BOOL MemWriteByte(DWORD address, BYTE data);

BOOL PortReadWord(DWORD address, WORD *pdata);
BOOL PortWriteWord(DWORD address, WORD data);
BOOL MemReadWord(DWORD address, WORD *pdata);
BOOL MemWriteWord(DWORD address, WORD data);

BOOL PortReadDword(DWORD address, DWORD *pdata);
BOOL PortWriteDword(DWORD address, DWORD data);
BOOL MemReadDword(DWORD address, DWORD *pdata);
BOOL MemWriteDword(DWORD address, DWORD data);

BOOL RegRead(DWORD offset, DWORD *pdata);
BOOL RegWrite(DWORD offset, DWORD data);

BOOL EnableIntr();
BOOL DisableIntr();

BOOL EnableDmaFinishedNotify();
BOOL DisableDmaFinishedNotify();

BOOL RegisterLocalISR(ISR_ROUTINE pfuncISR);
BOOL RegisterDmaFinishedSR(DMAFSR_ROUTINE pfuncDMAFSR);

BOOL DmaCommonBufferGet(DWORD *pdwPhyMemAddr, DWORD *pdwUserAddr, DWORD *pdwSize);
BOOL DmaChannelOpen(BOOL fDemandMode,unsigned int Threshold=2,unsigned int BusWidth=0);
BOOL DmaChannelClose();
BOOL DmaTransferHostToLocal(DWORD dwPhyMemAddr, DWORD dwLocalAddr, DWORD dwBytes);
BOOL DmaTransferLocalToHost(DWORD dwLocalAddr, DWORD dwPhyMemAddr, DWORD dwBytes);


/*
 * registers
 */

#define PCI9054_REG_BASE    0x000

/* PCI Configuration Registers */
#define PCI9054_VENDOR_ID            CFG_VENDOR_ID
#define PCI9054_COMMAND              CFG_COMMAND
#define PCI9054_REV_ID               CFG_REV_ID
#define PCI9054_CACHE_SIZE           CFG_CACHE_SIZE
#define PCI9054_RTR_BASE             CFG_BAR0
#define PCI9054_RTR_IO_BASE          CFG_BAR1
#define PCI9054_LOCAL_BASE0          CFG_BAR2
#define PCI9054_LOCAL_BASE1          CFG_BAR3
#define PCI9054_UNUSED_BASE1         CFG_BAR4
#define PCI9054_UNUSED_BASE2         CFG_BAR5
#define PCI9054_CIS_PTR              CFG_CIS_PTR
#define PCI9054_SUB_ID               CFG_SUB_VENDOR_ID
#define PCI9054_EXP_ROM_BASE         CFG_EXP_ROM_BASE
#define PCI9054_CAP_PTR              CFG_CAP_PTR
#define PCI9054_RESERVED2            CFG_RESERVED1
#define PCI9054_INT_LINE             CFG_INT_LINE

#define PCI9054_PM_CAP_ID            0x040
#define PCI9054_PM_CSR               0x044
#define PCI9054_HS_CAP_ID            0x048
#define PCI9054_VPD_CAP_ID           0x04C
#define PCI9054_VPD_DATA             0x050


/* Local Configuration Registers */
#define PCI9054_SPACE0_RANGE         (PCI9054_REG_BASE + 0x000)
#define PCI9054_SPACE0_REMAP         (PCI9054_REG_BASE + 0x004)
#define PCI9054_LOCAL_DMA_ARBIT      (PCI9054_REG_BASE + 0x008)
#define PCI9054_ENDIAN_DESC          (PCI9054_REG_BASE + 0x00C)
#define PCI9054_EXP_ROM_RANGE        (PCI9054_REG_BASE + 0x010)
#define PCI9054_EXP_ROM_REMAP        (PCI9054_REG_BASE + 0x014)
#define PCI9054_SPACE0_ROM_DESC      (PCI9054_REG_BASE + 0x018)
#define PCI9054_DM_RANGE             (PCI9054_REG_BASE + 0x01C)
#define PCI9054_DM_MEM_BASE          (PCI9054_REG_BASE + 0x020)
#define PCI9054_DM_IO_BASE           (PCI9054_REG_BASE + 0x024)
#define PCI9054_DM_PCI_MEM_REMAP     (PCI9054_REG_BASE + 0x028)
#define PCI9054_DM_PCI_IO_CONFIG     (PCI9054_REG_BASE + 0x02C)
#define PCI9054_SPACE1_RANGE         (PCI9054_REG_BASE + 0x0F0)
#define PCI9054_SPACE1_REMAP         (PCI9054_REG_BASE + 0x0F4)
#define PCI9054_SPACE1_DESC          (PCI9054_REG_BASE + 0x0F8)
#define PCI9054_DM_DAC               (PCI9054_REG_BASE + 0x0FC)


/* Runtime Registers */
#define PCI9054_MAILBOX0         0x078
#define PCI9054_MAILBOX1         0x07C

#define PCI9054_MAILBOX2             (PCI9054_REG_BASE + 0x048)
#define PCI9054_MAILBOX3             (PCI9054_REG_BASE + 0x04C)
#define PCI9054_MAILBOX4             (PCI9054_REG_BASE + 0x050)
#define PCI9054_MAILBOX5             (PCI9054_REG_BASE + 0x054)
#define PCI9054_MAILBOX6             (PCI9054_REG_BASE + 0x058)
#define PCI9054_MAILBOX7             (PCI9054_REG_BASE + 0x05C)
#define PCI9054_LOCAL_DOORBELL       (PCI9054_REG_BASE + 0x060)
#define PCI9054_PCI_DOORBELL         (PCI9054_REG_BASE + 0x064)
#define PCI9054_INT_CTRL_STAT        (PCI9054_REG_BASE + 0x068)
#define PCI9054_EEPROM_CTRL_STAT     (PCI9054_REG_BASE + 0x06C)
#define PCI9054_PERM_VENDOR_ID       (PCI9054_REG_BASE + 0x070)
#define PCI9054_REVISION_ID          (PCI9054_REG_BASE + 0x074)


/* DMA Registers */
#define PCI9054_DMA0_MODE            (PCI9054_REG_BASE + 0x080)
#define PCI9054_DMA0_PCI_ADDR        (PCI9054_REG_BASE + 0x084)
#define PCI9054_DMA0_LOCAL_ADDR      (PCI9054_REG_BASE + 0x088)
#define PCI9054_DMA0_COUNT           (PCI9054_REG_BASE + 0x08C)
#define PCI9054_DMA0_DESC_PTR        (PCI9054_REG_BASE + 0x090)
#define PCI9054_DMA1_MODE            (PCI9054_REG_BASE + 0x094)
#define PCI9054_DMA1_PCI_ADDR        (PCI9054_REG_BASE + 0x098)
#define PCI9054_DMA1_LOCAL_ADDR      (PCI9054_REG_BASE + 0x09C)
#define PCI9054_DMA1_COUNT           (PCI9054_REG_BASE + 0x0A0)
#define PCI9054_DMA1_DESC_PTR        (PCI9054_REG_BASE + 0x0A4)
#define PCI9054_DMA_COMMAND_STAT     (PCI9054_REG_BASE + 0x0A8)
#define PCI9054_DMA_ARBIT            (PCI9054_REG_BASE + 0x0AC)
#define PCI9054_DMA_THRESHOLD        (PCI9054_REG_BASE + 0x0B0)
#define PCI9054_DMA0_PCI_DAC         (PCI9054_REG_BASE + 0x0B4)
#define PCI9054_DMA1_PCI_DAC         (PCI9054_REG_BASE + 0x0B8)


/* Messaging Unit Registers */
#define PCI9054_OUTPOST_INT_STAT     (PCI9054_REG_BASE + 0x030)
#define PCI9054_OUTPOST_INT_MASK     (PCI9054_REG_BASE + 0x034)
#define PCI9054_MU_CONFIG            (PCI9054_REG_BASE + 0x0C0)
#define PCI9054_FIFO_BASE_ADDR       (PCI9054_REG_BASE + 0x0C4)
#define PCI9054_INFREE_HEAD_PTR      (PCI9054_REG_BASE + 0x0C8)
#define PCI9054_INFREE_TAIL_PTR      (PCI9054_REG_BASE + 0x0CC)
#define PCI9054_INPOST_HEAD_PTR      (PCI9054_REG_BASE + 0x0D0)
#define PCI9054_INPOST_TAIL_PTR      (PCI9054_REG_BASE + 0x0D4)
#define PCI9054_OUTFREE_HEAD_PTR     (PCI9054_REG_BASE + 0x0D8)
#define PCI9054_OUTFREE_TAIL_PTR     (PCI9054_REG_BASE + 0x0DC)
#define PCI9054_OUTPOST_HEAD_PTR     (PCI9054_REG_BASE + 0x0E0)
#define PCI9054_OUTPOST_TAIL_PTR     (PCI9054_REG_BASE + 0x0E4)
#define PCI9054_FIFO_CTRL_STAT       (PCI9054_REG_BASE + 0x0E8)


/* Additional register defintions */
#define MAX_PCI9054_REG_OFFSET   (PCI9054_REG_BASE + 0x100)
#define PCI9054_IN_FIFO_PORT     0x040
#define PCI9054_OUT_FIFO_PORT    0x044