send_control.v

射频识别系统的rfid的发送控制模块的ｖｅｉｌｏｇ代码

module send_control(sample_clk,
                    syn_global_reset,
                    assert_2,
                    assert_4,
                    assert_10,
                    assert_16,
                    assert_32,
                    assert_8,
                    assert_63,
                    assert_7,
                    data_shift_encode,
                    qout_encode,
                    begin_encode,
                    read_over_reg,
                    write_over_reg,
                    set_count_send_final,
                    add_count_send,
                    shiftregs_move_1bit_send,
                    crc_generate_sample,
                    crc_shift_1bit,
                    send,
                    stop_encode,
                    send_over,
                    ena_regs_send,
                    ena_crc_send,
                    q_to_reader);
//recent modification:4/24
//output ports modified to internal ports:state,nextstate,set_count_send
input sample_clk;
input syn_global_reset;

input assert_2;
input assert_4;
input assert_10;
input assert_16;
input assert_32;
input assert_8;
input assert_63;
input assert_7;

input data_shift_encode;
input qout_encode;


input begin_encode;
input read_over_reg;
input write_over_reg;

reg [4:1] state;
reg [4:1] nextstate;

output set_count_send_final;

reg set_count_send;


output send;
output stop_encode;
output send_over;

output add_count_send;


output shiftregs_move_1bit_send;

output crc_generate_sample;

output crc_shift_1bit;


output ena_regs_send;
output ena_crc_send;

output q_to_reader;
reg q_to_reader;

parameter Wait=4'b0000,
          S1=4'b0001,
          S2=4'b0011,
          S3=4'b0010,
          S8=4'b0110,
          S9=4'b0111,
          S10=4'b0101,
          S11=4'b0100,
          S4=4'b1100,
          S5=4'b1101,
          S6=4'b1111,
          S7=4'b1110;
          

 wire assert_63_or_assert_7;
 assign assert_63_or_assert_7=(read_over_reg)?assert_63:
                                            (write_over_reg)?assert_7:1'b0;
 
          
always@(posedge sample_clk)
begin
    if(syn_global_reset)
      begin
          state<=Wait;
      end
    else
      begin
          state<=nextstate;
      end
end

always@(state or begin_encode or assert_2 or assert_32 or assert_4 or assert_10 or assert_7 or assert_16 or assert_8 or assert_63_or_assert_7 )
begin
    case(state)
        Wait: 
             begin
                 if(begin_encode)
                    begin
                        nextstate<=S1;
                    end
                 else
                    begin
                        nextstate<=Wait;
                    end
             end
        S1:
           begin
               if(assert_32)
                  begin
                      nextstate<=S2;
                  end
               else
                 begin
                     nextstate<=S1;
                 end
           end
        S2:
           begin
              nextstate<=S3;
           end       
        S3:
           begin
              if(assert_8)
                 begin
                     nextstate<=S8;
                 end
              else
                 begin
                     nextstate<=S2;
                 end
           end
        S8:
           begin
               if(assert_2)
                  begin
                      nextstate<=S9;
                  end
               else if(assert_10)
                  begin
                      nextstate<=S11;
                  end
               else
                  begin
                      nextstate<=S8;
                  end
           end
        S9:
           begin
               if(assert_4)
                  begin
                      nextstate<=S10;
                  end
               else if(assert_7)
                  begin
                      nextstate<=S8;
                  end
               else
                  begin
                      nextstate<=S9;
                  end
           end
        S10:
            begin
                nextstate<=S9;
            end
        S11:
            begin
                nextstate<=S4;
            end
        S4:
           begin
               if(assert_63_or_assert_7)
                  begin
                      nextstate<=S5;
                  end
               else
                  begin
                      nextstate<=S4;
                  end
           end

        S5:
           begin
              nextstate<=S6;
           end
        S6:
           begin
               if(assert_16)
                  begin
                      nextstate<=S7;
                  end
               else
                  begin
                      nextstate<=S6;
                  end
           end
        S7:
           begin
              nextstate<=S7;
           end
        default:
                 begin
                     nextstate<=Wait;
                 end
   endcase
end


assign set_count_send_final=begin_encode||set_count_send;
always@(state or assert_16 or assert_32 or assert_8)
begin
    case(state)
        S1:
           begin
               if(assert_32)
                  begin
                     set_count_send=1'b1;
                  end
               else
                  begin
                      set_count_send=1'b0;
                  end
           end
        S3:
           begin
               if(assert_8)
                  begin
                      set_count_send=1'b1;
                  end
               else
                  begin
                      set_count_send=1'b0;
                  end
           end
        S5:
           begin
               set_count_send=1'b1;
           end
        S6:
           begin
               if(assert_16)
                  begin
                       set_count_send=1'b1;
                  end
                else
                   begin
                       set_count_send=1'b0;
                   end
           end
        S11:
            begin
                set_count_send=1'b1;
            end
        default:
                begin
                    set_count_send=1'b0;
                end
    endcase
end


reg add_count_send_inter;
always@(state)
begin
    case(state)
        S1:
           begin
               add_count_send_inter=1'b1;
           end
        S2:
           begin
               add_count_send_inter=1'b1;
           end
        S8:
           begin
               add_count_send_inter=1'b1;
           end
        S9:
           begin
               add_count_send_inter=1'b1;
           end
        S10:
            begin
                add_count_send_inter=1'b1;
            end
        default:
                begin
                    add_count_send_inter=1'b0;
                end
    endcase
end

assign add_count_send=add_count_send_inter||data_shift_encode;


assign send=(state==S11);


assign stop_encode=(state==S6)&&(assert_16);


assign send_over=(state==S7)?1'b1:1'b0;


assign ena_regs_send=send||(state==S4)||(state==S5);
assign shiftregs_move_1bit_send=ena_regs_send&&data_shift_encode;
assign crc_generate_sample=ena_regs_send&&(~data_shift_encode);

assign ena_crc_send=(state==S6);
assign crc_shift_1bit=ena_crc_send&&data_shift_encode;


always@(state or qout_encode)
begin
    case(state)
        S1:
           begin
               q_to_reader=1'b0;
           end
        S2:
           begin
               q_to_reader=1'b0;
           end
        S3:
           begin
               q_to_reader=1'b1;
           end
        S8:
           begin
               q_to_reader=1'b0;
           end
        S9:
           begin
               q_to_reader=1'b1;
           end
        S10:
            begin
                q_to_reader=1'b0;
            end
        S11:
            begin
                q_to_reader=1'b1;
            end
        S4:
           begin
               q_to_reader=qout_encode;
           end
        S5:
           begin
               q_to_reader=qout_encode;
           end
        S6:
           begin
               q_to_reader=qout_encode;
           end
        S7:
           begin
               q_to_reader=1'b0;
           end
        Wait:
           begin
               q_to_reader=1'b0;
           end
        default:
                begin
                    q_to_reader=1'b0;
                end
    endcase
end

endmodule