decode.v

射频识别系统标签的解码模块的VERILOG代码

module decode(sample_clk,
              reset,
              syn_global_reset,
              begin_decode,
              syn_data_in,
              stop_receive,
              q_out_decode,
              add_count_decode,
              read_in,
              code_error);
//recent modification:5/10
//output ports modified to internal ports:state,nextstate
input sample_clk;
input reset;
input syn_global_reset;
input begin_decode;
input syn_data_in;
input stop_receive;

reg [3:1] state;
reg [3:1] nextstate;

output q_out_decode;
reg q_out_decode;

output add_count_decode;
output read_in;
output code_error;

parameter Wait=3'b000,
          S1=3'b001,
          S2=3'b010,
          S3=3'b011,
          CODING_ERROR=3'b111;

always@(posedge sample_clk or negedge reset)
begin
    if(!reset)
       begin
           state<=Wait;
       end
    else if(syn_global_reset)
       begin
           state<=Wait;
       end
    else if(begin_decode)
       begin
           state<=S1;
       end
    else
       begin
           state<=nextstate;
       end
end

always@(state or syn_data_in or stop_receive)
begin
    case(state)
        S1:
           begin
               if(stop_receive)
                  begin
                      nextstate<=Wait;
                  end
               else 
                 begin
                    case(syn_data_in)
                      1'b1:
                            begin
                               nextstate<=S2;
                            end
                      1'b0:
                            begin
                               nextstate<=S3;
                            end
                      default:
                               begin
                                  nextstate<=S1;
                               end
                      endcase
                 end
           end
        S2:
           begin
               if(syn_data_in==1'b1)
                  begin
                      nextstate<=CODING_ERROR;
                  end
               else
                  begin
                      nextstate<=S1;
                  end
           end
        S3:
           begin
               if(syn_data_in==1'b0)
                  begin
                      nextstate<=CODING_ERROR;
                  end
               else
                  begin
                      nextstate<=S1;
                  end
           end
        Wait:
             begin
                  nextstate<=Wait;
             end
        CODING_ERROR:
                   begin
                       nextstate<=Wait;
                   end
        default:
                begin
                    nextstate<=Wait;
                end
    endcase
end

assign add_count_decode=(state==S2)||(state==S3);
assign read_in=(state==S1);
assign code_error=(state==CODING_ERROR);

wire set_qout_0;
wire set_qout_1;
assign set_qout_0=(state==S3);
assign set_qout_1=(state==S2);

always@(negedge sample_clk)
begin
    if(set_qout_0||begin_decode)
       begin
           q_out_decode<=1'b0;
       end
    else if(set_qout_1)
       begin
           q_out_decode<=1'b1;
       end
end
endmodule