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/*
* S3C44B0X ROM monitor startup code for CYGNU compiler
* 2001-10-29, by Gai, Feng
*
* 1. Vectored mode interrupt vector table at 0x0c000000
* 2. Real vectored for monitor at ( TOP_RAM - 1MB )
* 3. setup C env, and jump to main entry
*
* RAM vector structure at 0x0c000000, just jump to ( TOP_RAM - 1MB )
* 1. 32 bytes per vector entry
* 2. vector list:
* 0 - reset handler
* 1 - Undefined instruction entry
* 2 - SWI entry
* 3 - Prefetch abort entry
* 4 - Data abort entry
* 5 - reserved
* 6 - IRQ entry ( not used in int controller vectored mode )
* 7 - FIQ entry ( not used )
* 8-33 - LISR 0 - LISR 25
*
* Real vector at ( TOP_RAM - 1MB )
* 1. 32 bytes per vector entry
* 2. vector list:
* same as above
*/
.equ LOCKOUT, 0xC0 /* Interrupt lockout value */
.equ LOCK_MSK, 0xC0 /* Interrupt lockout mask value */
.equ MODE_MASK, 0x1F /* Processor Mode Mask */
.equ SUP_MODE, 0x13 /* Supervisor Mode (SVC) */
.global monitor_entry
.global __bss_start__
.global __bss_end__
.global _start
.global INT_UNDEFINE
.global INT_SWI_PARSE
.global INT_PREF_ABORT
.global INT_DATA_ABORT
.global INT_IRQ_PARSE
.global INT_FIQ_PARSE
.global INT_RESERVE
.global TCC_Dispatch_LISR
.global TCT_Interrupt_Context_Save
.global TCT_Interrupt_Context_Restore
.global TMT_Timer_Interrupt
.text
_start:
b startup /* 0 - Reset vector */
.space 28
b INT_UNDEFINE /* 1 - Undefined instruction */
.space 28
b INT_SWI_PARSE /* 2 - SWI */
.space 28
b INT_PREF_ABORT /* 3 - Prefetch abort */
.space 28
b INT_DATA_ABORT /* 4 - Data abort */
.space 28
/* startup 5 - reserved */
b INT_RESERVE
.space 28
b INT_IRQ_PARSE /* 6 - IRQ */
.space 28
b INT_FIQ_PARSE /* 7 - FIQ */
.space 28
/* 8 - LISR 0 EINT0 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #0
bl TCC_Dispatch_LISR @ dispatch_lisr( 0 )
mov a1, #0x02000000
b end_of_irq
.space 4
/* 9 - LISR 1 EINT1 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #1
bl TCC_Dispatch_LISR @ dispatch_lisr( 1 )
mov a1, #0x01000000
b end_of_irq
.space 4
/* 10- LISR 2 EINT2 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #2
bl TCC_Dispatch_LISR @ dispatch_lisr( 2 )
mov a1, #0x00800000
b end_of_irq
.space 4
/* 11- LISR 3 EINT3 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #3
bl TCC_Dispatch_LISR @ dispatch_lisr( 3 )
mov a1, #0x00400000
b end_of_irq
.space 4
/* 12- LISR 4 EINT4567 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #4
bl TCC_Dispatch_LISR @ dispatch_lisr( 4 )
mov a1, #0x00200000
b end_of_irq
.space 4
/* 13- LISR 5 TICK */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #5
bl TCC_Dispatch_LISR @ dispatch_lisr( 5 )
mov a1, #0x00100000
b end_of_irq
.space 4
/* 14- LISR 6 ZDMA0 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #6
bl TCC_Dispatch_LISR @ dispatch_lisr( 6 )
mov a1, #0x00080000
b end_of_irq
.space 4
/* 15- LISR 7 ZDMA1 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #7
bl TCC_Dispatch_LISR @ dispatch_lisr( 7 )
mov a1, #0x00040000
b end_of_irq
.space 4
/* 16- LISR 8 BDMA0 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #8
bl TCC_Dispatch_LISR @ dispatch_lisr( 8 )
mov a1, #0x00020000
b end_of_irq
.space 4
/* 17- LISR 9 BDMA1 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #9
bl TCC_Dispatch_LISR @ dispatch_lisr( 9 )
mov a1, #0x00010000
b end_of_irq
.space 4
/* 18- LISR 10 WDT */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #0
bl TCC_Dispatch_LISR @ dispatch_lisr( 10 )
mov a1, #0x00008000
b end_of_irq
.space 4
/* 19- LISR 11 UERR */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #11
bl TCC_Dispatch_LISR @ dispatch_lisr( 11 )
mov a1, #0x00004000
b end_of_irq
.space 4
/* 20- LISR 12 TIMER0 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #12
bl TCC_Dispatch_LISR @ dispatch_lisr( 12 )
mov a1, #0x00002000
b end_of_irq
.space 4
/* 21- LISR 13 TIMER1 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #13
bl TCC_Dispatch_LISR @ dispatch_lisr( 13 )
mov a1, #0x00001000
b end_of_irq
.space 4
/* 22- LISR 14 TIMER2 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #14
bl TCC_Dispatch_LISR @ dispatch_lisr( 14 )
mov a1, #0x00000800
b end_of_irq
.space 4
/* 23- LISR 15 TIMER3 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #15
bl TCC_Dispatch_LISR @ dispatch_lisr( 15 )
mov a1, #0x00000400
b end_of_irq
.space 4
/* 24- LISR 16 TIMER4 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #16
bl TCC_Dispatch_LISR @ dispatch_lisr( 16 )
mov a1, #0x00000200
b end_of_irq
.space 4
/* 25- LISR 17 TIMER5 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
bl TMT_Timer_Interrupt @ timer tick interrupt
mov a1, #0x00000100
b end_of_irq
.space 8
/* 26- LISR 18 URXD0 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #18
bl TCC_Dispatch_LISR @ dispatch_lisr( 18 )
mov a1, #0x00000080
b end_of_irq
.space 4
/* 27- LISR 19 URXD1 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #19
bl TCC_Dispatch_LISR @ dispatch_lisr( 19 )
mov a1, #0x00000040
b end_of_irq
.space 4
/* 28- LISR 20 IIC */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #20
bl TCC_Dispatch_LISR @ dispatch_lisr( 20 )
mov a1, #0x00000020
b end_of_irq
.space 4
/* 29- LISR 21 SIO */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #21
bl TCC_Dispatch_LISR @ dispatch_lisr( 21 )
mov a1, #0x00000010
b end_of_irq
.space 4
/* 30- LISR 22 UTXD0 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #22
bl TCC_Dispatch_LISR @ dispatch_lisr( 22 )
mov a1, #0x00000008
b end_of_irq
.space 4
/* 31- LISR 23 UTXD1 */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #23
bl TCC_Dispatch_LISR @ dispatch_lisr( 23 )
mov a1, #0x00000004
b end_of_irq
.space 4
/* 32- LISR 24 RTC */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #24
bl TCC_Dispatch_LISR @ dispatch_lisr( 24 )
mov a1, #0x00000002
b end_of_irq
.space 4
/* 33- LISR 25 ADC */
stmdb sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack
sub a4,lr,#4 @ Save IRQ's lr (return address)
bl TCT_Interrupt_Context_Save @ Call context save routine
mov a1, #25
bl TCC_Dispatch_LISR @ dispatch_lisr( 25 )
mov a1, #0x00000001
b end_of_irq
.space 4
end_of_irq:
mov a2, #0x01e00000
add a2, a2, #0x24 @ I_ISPC @ 0x01e00024
str a1, [a2] @ clear pending intr bit
mov a2, #0x01d80000
add a2, a2, #4 @ CLKCON @ 0x01d80004
ldr a1, [a2]
bic a1, a1, #4 @ clear IDLE bit
str a1, [a2]
b TCT_Interrupt_Context_Restore
/*******************************/
startup:
@
@ Clear the un-initialized global and static C data areas
@
@if( *(uint32 *)0x00000274 != 0 )
ldr a1, =0x00000274
ldr a2, [a1]
cmp a2, #0
beq fixed
@{
@*(uint32 *)0x01C80028 = 0;
ldr a1, =0x01C80028
ldr a2, =0x00
str a2, [a1]
@*(uint32 *)0x1d20040 = 0x04;
ldr a1, =0x1d20040
ldr a2, =0x04
str a2, [a1]
@*(uint32 *)0x1d20044 = 0xbb;
ldr a1, =0x1d20044
ldr a2, =0xbb
str a2, [a1]
@*(uint16 *)(0x555<<1) = 0xaa;
ldr a1, =0x555<<1
ldr a2, =0xaa
strh a2, [a1]
@*(uint16 *)(0x2aa<<1) = 0x55;
ldr a1, =0x2aa<<1
ldr a2, =0x55
strh a2, [a1]
@*(uint16 *)(0x555<<1) = 0xa0;
ldr a1, =0x555<<1
ldr a2, =0xa0
strh a2, [a1]
@*(uint16 *)0x00000274 = 0;
ldr a1, =0x00000274
ldr a2, =0x00
strh a2, [a1]
@*(uint16 *)0x00000000 = 0xf0; // reset
ldr a1, =0x00000000
ldr a2, =0xf0
strh a2, [a1]
@}
fixed:
ldr a1,=__bss_start__ @ Pickup the start of the BSS area
mov a3,#0 @ Clear value in a3
ldr a2,=__bss_end__ @ Pickup the end of the BSS area
clear_loop:
str a3,[a1],#4 @ Clear a word, a1 += 4
cmp a1,a2 @ end of bss ?
bne clear_loop @ If not, continue with the BSS clear
@
@ disable cache
@
mov a1, #0x01c00000 @ SYSCFG
ldr a2, [a1]
bic a2, a2, #6 @ disable cache
str a2, [a1] @ modify SYSCFG
@
@ flush cache
@
mov a3, #0x10000000
add a3, a3, #0x2000 @ a3 = start of LRU ram
mov a4, #0x10000000
add a4, a4, #0x4800 @ a4 = end of LRM ram
mov a2, #0
flush_one_tag:
str a2, [a3]
add a3, a3, #0x10 @ next
cmp a3, a4
bne flush_one_tag
@
@ setup non-cache area
@
mov a1, #0x01c00000 @ SYSCFG
mov a2, #0x00000000 @ start = 0x0000 0000
add a2, a2, #0xc0000000 @ end = 0x0c00 0000
str a2, [a1, #4] @ NCACHE0
mov a1, #0x01c00000 @ SYSCFG
mov a2, #0x0000e000 @ start = 0x0e00 0000
add a2, a2, #0xf0000000 @ end = 0x0f00 0000
str a2, [a1, #8] @ NCACHE1
@
@ re-enable cache
@
mov a1, #0x01c00000 @ SYSCFG
ldr a2, [a1]
orr a2, a2, #0x06 @ enable all 8K cache, and disable write buffer
str a2, [a1] @ modify SYSCFG
ldr pc,=INT_Initialize
/* define irq_entry() for int.s */
.global irq_entry
irq_entry:
b irq_entry
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