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📄 240t.map.rpt

📁 很好的一个东西,希望能对大家有所帮助.关于PWM的编程.
💻 RPT
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; LPM_PIPELINE           ; 0        ; Untyped                                                       ;
; CHAIN_SIZE             ; 8        ; Untyped                                                       ;
; ONE_INPUT_IS_CONSTANT  ; YES      ; Untyped                                                       ;
; CARRY_CHAIN            ; MANUAL   ; Untyped                                                       ;
; CASCADE_CHAIN          ; MANUAL   ; Untyped                                                       ;
; CARRY_CHAIN_LENGTH     ; 48       ; CARRY_CHAIN_LENGTH                                            ;
; CASCADE_CHAIN_LENGTH   ; 2        ; CASCADE_CHAIN_LENGTH                                          ;
; DEVICE_FAMILY          ; MAX II   ; Untyped                                                       ;
; CBXI_PARAMETER         ; cmpr_hti ; Untyped                                                       ;
; AUTO_CARRY_CHAINS      ; ON       ; AUTO_CARRY                                                    ;
; IGNORE_CARRY_BUFFERS   ; OFF      ; IGNORE_CARRY                                                  ;
; AUTO_CASCADE_CHAINS    ; ON       ; AUTO_CASCADE                                                  ;
; IGNORE_CASCADE_BUFFERS ; OFF      ; IGNORE_CASCADE                                                ;
+------------------------+----------+---------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_constant0:inst8|lpm_constant:lpm_constant_component ;
+--------------------+------------------+--------------------------------------------------------------+
; Parameter Name     ; Value            ; Type                                                         ;
+--------------------+------------------+--------------------------------------------------------------+
; LPM_WIDTH          ; 5                ; Signed Integer                                               ;
; LPM_CVALUE         ; 1                ; Signed Integer                                               ;
; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                      ;
; CBXI_PARAMETER     ; lpm_constant_8e6 ; Untyped                                                      ;
+--------------------+------------------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Apr 09 08:20:22 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 240t -c 240t
Info: Found 1 design units, including 1 entities, in source file 240t.bdf
    Info: Found entity 1: 240t
Info: Found 1 design units, including 1 entities, in source file 240t.v
    Info: Found entity 1: t240t
Info: Found 1 design units, including 1 entities, in source file leddrv.v
    Info: Found entity 1: leddrv
Info: Found 1 design units, including 1 entities, in source file pwmon.v
    Info: Found entity 1: pwmon
Info: Found 1 design units, including 1 entities, in source file uarts.v
    Info: Found entity 1: uarts
Info: Found 1 design units, including 1 entities, in source file uartr.v
    Info: Found entity 1: uartr
Info: Found 1 design units, including 1 entities, in source file sevenseg.v
    Info: Found entity 1: sevenseg
Info: Found 1 design units, including 1 entities, in source file pwm.v
    Info: Found entity 1: pwm
Info: Found 1 design units, including 1 entities, in source file civ.v
    Info: Found entity 1: civ
Info: Elaborating entity "240t" for the top level hierarchy
Warning: Processing legacy GDF or BDF entity "240t" with Max+Plus II bus and instance naming rules
Warning: Pin "clk" not connected
Warning: Using design file lpm_compare0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_compare0
Info: Elaborating entity "lpm_compare0" for hierarchy "lpm_compare0:inst3"
Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/lpm_compare.tdf
    Info: Found entity 1: lpm_compare
Info: Elaborating entity "lpm_compare" for hierarchy "lpm_compare0:inst3|lpm_compare:lpm_compare_component"
Info: Elaborated megafunction instantiation "lpm_compare0:inst3|lpm_compare:lpm_compare_component"
Info: Found 1 design units, including 1 entities, in source file db/cmpr_75i.tdf
    Info: Found entity 1: cmpr_75i
Info: Elaborating entity "cmpr_75i" for hierarchy "lpm_compare0:inst3|lpm_compare:lpm_compare_component|cmpr_75i:auto_generated"
Info: Elaborating entity "civ" for hierarchy "civ:inst6"
Warning (10230): Verilog HDL assignment warning at civ.v(8): truncated value with size 32 to match size of target (11)
Warning: Using design file altufm_osc0.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project
    Info: Found entity 1: altufm_osc0_altufm_osc_rv5
    Info: Found entity 2: altufm_osc0
Info: Elaborating entity "altufm_osc0" for hierarchy "altufm_osc0:inst10"
Info: Elaborating entity "altufm_osc0_altufm_osc_rv5" for hierarchy "altufm_osc0:inst10|altufm_osc0_altufm_osc_rv5:altufm_osc0_altufm_osc_rv5_component"
Warning: Using design file lpm_counter0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_counter0
Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst"
Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "lpm_counter0:inst|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_6mh.tdf
    Info: Found entity 1: cntr_6mh
Info: Elaborating entity "cntr_6mh" for hierarchy "lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_6mh:auto_generated"
Warning: Using design file lpm_compare1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_compare1
Info: Elaborating entity "lpm_compare1" for hierarchy "lpm_compare1:inst5"
Info: Elaborating entity "lpm_compare" for hierarchy "lpm_compare1:inst5|lpm_compare:lpm_compare_component"
Info: Elaborated megafunction instantiation "lpm_compare1:inst5|lpm_compare:lpm_compare_component"
Info: Found 1 design units, including 1 entities, in source file db/cmpr_hti.tdf
    Info: Found entity 1: cmpr_hti
Info: Elaborating entity "cmpr_hti" for hierarchy "lpm_compare1:inst5|lpm_compare:lpm_compare_component|cmpr_hti:auto_generated"
Warning: Using design file lpm_dff0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_dff0
Info: Elaborating entity "lpm_dff0" for hierarchy "lpm_dff0:inst7"
Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/lpm_ff.tdf
    Info: Found entity 1: lpm_ff
Info: Elaborating entity "lpm_ff" for hierarchy "lpm_dff0:inst7|lpm_ff:lpm_ff_component"
Info: Elaborated megafunction instantiation "lpm_dff0:inst7|lpm_ff:lpm_ff_component"
Warning: Using design file lpm_counter1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_counter1
Info: Elaborating entity "lpm_counter1" for hierarchy "lpm_counter1:inst2"
Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter1:inst2|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "lpm_counter1:inst2|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_jli.tdf
    Info: Found entity 1: cntr_jli
Info: Elaborating entity "cntr_jli" for hierarchy "lpm_counter1:inst2|lpm_counter:lpm_counter_component|cntr_jli:auto_generated"
Warning: Using design file lpm_constant0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_constant0
Info: Elaborating entity "lpm_constant0" for hierarchy "lpm_constant0:inst8"
Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/lpm_constant.tdf
    Info: Found entity 1: lpm_constant
Info: Elaborating entity "lpm_constant" for hierarchy "lpm_constant0:inst8|lpm_constant:lpm_constant_component"
Info: Elaborated megafunction instantiation "lpm_constant0:inst8|lpm_constant:lpm_constant_component"
Info: Converted 2 single input CARRY primitives to CARRY_SUM primitives
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "clk"
Info: Implemented 40 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 4 output pins
    Info: Implemented 33 logic cells
    Info: Implemented 1 User Flash Memory blocks
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Allocated 141 megabytes of memory during processing
    Info: Processing ended: Wed Apr 09 08:20:27 2008
    Info: Elapsed time: 00:00:05


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