segmen4to7.vhd

来自「用硬件描述语言(或混合原理图)设计模24计数器模块、4-7显示译码模块、顶层模块」· VHDL 代码 · 共 38 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY segmen4to7 IS
PORT (i: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	  a,b,c,d,e,f,g: OUT STD_LOGIC);
END segmen4to7;

ARCHITECTURE rtl OF segmen4to7 IS
SIGNAL y: STD_LOGIC_VECTOR (6 DOWNTO 0);
BEGIN
a<=y(6);
b<=y(5);
c<=y(4);
d<=y(3);
e<=y(2);
f<=y(1);
g<=y(0);
PROCESS (i)
BEGIN
	CASE  i IS
	WHEN "0000"=>y<="0000001";
	WHEN "0001"=>y<="1001111";
	WHEN "0010"=>y<="0010010";
	WHEN "0011"=>y<="0000110";
	WHEN "0100"=>y<="1001100";
	WHEN "0101"=>y<="0100100";
	WHEN "0110"=>y<="0100000";
	WHEN "0111"=>y<="0001111";
	WHEN "1000"=>y<="0000000";
	WHEN "1001"=>y<="0000100";

	WHEN  OTHERS=>y<="XXXXXXX";
	END CASE;
END PROCESS;
END rtl;