📄 mo60.rpt
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(31) 26 B SOFT t 0 0 0 0 2 1 0 |LPM_ADD_SUB:178|addcore:adder|addcore:adder0|result_node1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\top\mo60.rpt
mo60
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------- LC23 cout
| +----------------- LC25 H0
| | +--------------- LC24 H1
| | | +------------- LC22 H2
| | | | +----------- LC21 H3
| | | | | +--------- LC26 |LPM_ADD_SUB:178|addcore:adder|addcore:adder0|result_node1
| | | | | | +------- LC20 L0
| | | | | | | +----- LC19 L1
| | | | | | | | +--- LC18 L2
| | | | | | | | | +- LC17 L3
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC23 -> * - - - - - - - - - | - * | <-- cout
LC25 -> * * * * - - - - - - | - * | <-- H0
LC24 -> * * * * - - - * - * | - * | <-- H1
LC22 -> * * * * - - - * - * | - * | <-- H2
LC21 -> * * * * * - - * - * | - * | <-- H3
LC26 -> - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:178|addcore:adder|addcore:adder0|result_node1
LC20 -> * * * * - * * * * * | - * | <-- L0
LC19 -> * * * * - * - * * * | - * | <-- L1
LC18 -> * * * * - - - * * * | - * | <-- L2
LC17 -> * * * * - - - * - * | - * | <-- L3
Pin
43 -> - - - - - - - - - - | - - | <-- clk
4 -> * * * * - - * * * * | - * | <-- en
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\top\mo60.rpt
mo60
** EQUATIONS **
clk : INPUT;
en : INPUT;
-- Node name is 'cout' = ':3'
-- Equation name is 'cout', type is output
cout = DFFE( _EQ001 $ !en, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = en & H0 & !H1 & H2 & !H3 & L0 & !L1 & !L2 & L3
# cout & en & !H2 & !H3 & L0 & !L1 & !L2 & L3
# cout & en & !H1 & !H3 & L0 & !L1 & !L2 & L3
# !cout & !en;
-- Node name is 'H0' = 'hq0'
-- Equation name is 'H0', location is LC025, type is output.
H0 = TFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = en & H0 & !H1 & H2 & !H3 & L0 & !L1 & !L2 & L3
# en & !H0 & !H1 & !H3 & L0 & !L1 & !L2 & L3
# en & !H2 & !H3 & L0 & !L1 & !L2 & L3;
-- Node name is 'H1' = 'hq1'
-- Equation name is 'H1', location is LC024, type is output.
H1 = TFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = en & H0 & !H2 & !H3 & L0 & !L1 & !L2 & L3;
-- Node name is 'H2' = 'hq2'
-- Equation name is 'H2', location is LC022, type is output.
H2 = TFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = en & H0 & H1 & !H2 & !H3 & L0 & !L1 & !L2 & L3
# en & H0 & !H1 & H2 & !H3 & L0 & !L1 & !L2 & L3;
-- Node name is 'H3' = 'hq3'
-- Equation name is 'H3', location is LC021, type is output.
H3 = TFFE( GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'L0' = 'lq0'
-- Equation name is 'L0', location is LC020, type is output.
L0 = TFFE( en, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'L1' = 'lq1'
-- Equation name is 'L1', location is LC019, type is output.
L1 = DFFE( _EQ005 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !H1 & !H3 & L0 & !L1 & !L2 & L3
# !H2 & !H3 & L0 & !L1 & !L2 & L3
# en & !_LC026
# !en & !L1;
-- Node name is 'L2' = 'lq2'
-- Equation name is 'L2', location is LC018, type is output.
L2 = TFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = en & L0 & L1;
-- Node name is 'L3' = 'lq3'
-- Equation name is 'L3', location is LC017, type is output.
L3 = TFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = en & !H2 & !H3 & L0 & !L1 & !L2 & L3 & _X001
# en & !H1 & !H3 & L0 & !L1 & !L2 & L3 & _X001
# en & L0 & L1 & L2;
_X001 = EXP( L0 & L1 & L2);
-- Node name is '|LPM_ADD_SUB:178|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried
_LC026 = LCELL( L1 $ L0);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\top\mo60.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,581K
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