📄 mo24.rpt
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| | | | | | | +----------------- LC30 ha
| | | | | | | | +--------------- LC32 hb
| | | | | | | | | +------------- LC28 hc
| | | | | | | | | | +----------- LC22 hd
| | | | | | | | | | | +--------- LC23 he
| | | | | | | | | | | | +------- LC24 hf
| | | | | | | | | | | | | +----- LC25 hg
| | | | | | | | | | | | | | +--- LC26 lb
| | | | | | | | | | | | | | | +- LC27 lc
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC18 -> * * * - * * * - - - - - - - * * | * * | <-- |COUNT24:3|lq3
LC19 -> * * * - * * * - - - - - - - * * | * * | <-- |COUNT24:3|lq2
LC20 -> * * * - * * * - - - - - - - * * | * * | <-- |COUNT24:3|lq1
LC21 -> * * * * * * * - - - - - - - * * | * * | <-- |COUNT24:3|lq0
LC31 -> * * * - * * * * * * * * * * - - | - * | <-- |COUNT24:3|hq1
LC29 -> * * - - * * * * * * * * * * - - | - * | <-- |COUNT24:3|hq0
LC17 -> - - - - - - * - - - - - - - - - | - * | <-- cout
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
4 -> * * * * * * * - - - - - - - - - | - * | <-- en
LC16 -> - * - - - - - - - - - - - - - - | - * | <-- |COUNT24:3|LPM_ADD_SUB:178|addcore:adder|addcore:adder0|result_node2
LC13 -> * - - - - - - - - - - - - - - - | - * | <-- |COUNT24:3|LPM_ADD_SUB:178|addcore:adder|addcore:adder0|result_node3
LC12 -> * * * - * * * * * * * * * * - - | - * | <-- |COUNT24:3|hq3
LC8 -> * * * - * * * * * * * * * * - - | - * | <-- |COUNT24:3|hq2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\top\mo24.rpt
mo24
** EQUATIONS **
clk : INPUT;
en : INPUT;
-- Node name is 'cout' = '|COUNT24:3|:3'
-- Equation name is 'cout', type is output
cout = DFFE( _EQ001 $ !en, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = en & !_LC008 & !_LC012 & !_LC018 & !_LC019 & _LC020 & _LC021 &
!_LC029 & _LC031
# cout & en & !_LC008 & !_LC012 & _LC018 & !_LC019 & !_LC020 &
_LC021 & !_LC031
# !cout & !en;
-- Node name is 'ha'
-- Equation name is 'ha', location is LC030, type is output.
ha = LCELL( _EQ002 $ GND);
_EQ002 = _LC008 & !_LC012 & !_LC029 & !_LC031
# !_LC008 & !_LC012 & _LC029 & !_LC031;
-- Node name is 'hb'
-- Equation name is 'hb', location is LC032, type is output.
hb = LCELL( _EQ003 $ GND);
_EQ003 = _LC008 & !_LC012 & !_LC029 & _LC031
# _LC008 & !_LC012 & _LC029 & !_LC031;
-- Node name is 'hc'
-- Equation name is 'hc', location is LC028, type is output.
hc = LCELL( _EQ004 $ GND);
_EQ004 = !_LC008 & !_LC012 & !_LC029 & _LC031;
-- Node name is 'hd'
-- Equation name is 'hd', location is LC022, type is output.
hd = LCELL( _EQ005 $ GND);
_EQ005 = _LC008 & !_LC012 & _LC029 & _LC031
# _LC008 & !_LC012 & !_LC029 & !_LC031
# !_LC008 & !_LC012 & _LC029 & !_LC031;
-- Node name is 'he'
-- Equation name is 'he', location is LC023, type is output.
he = LCELL( _EQ006 $ !_LC012);
_EQ006 = !_LC008 & _LC012 & _LC029 & !_LC031
# !_LC012 & !_LC029 & _LC031
# !_LC008 & !_LC012 & !_LC029;
-- Node name is 'hf'
-- Equation name is 'hf', location is LC024, type is output.
hf = LCELL( _EQ007 $ !_LC012);
_EQ007 = _LC008 & !_LC012 & !_LC029
# _LC008 & !_LC012 & !_LC031
# !_LC012 & !_LC029 & !_LC031;
-- Node name is 'hg'
-- Equation name is 'hg', location is LC025, type is output.
hg = LCELL( _EQ008 $ GND);
_EQ008 = _LC008 & !_LC012 & _LC029 & _LC031
# !_LC008 & !_LC012 & !_LC031;
-- Node name is 'la'
-- Equation name is 'la', location is LC002, type is output.
la = LCELL( _EQ009 $ GND);
_EQ009 = !_LC018 & _LC019 & !_LC020 & !_LC021
# !_LC018 & !_LC019 & !_LC020 & _LC021;
-- Node name is 'lb'
-- Equation name is 'lb', location is LC026, type is output.
lb = LCELL( _EQ010 $ GND);
_EQ010 = !_LC018 & _LC019 & _LC020 & !_LC021
# !_LC018 & _LC019 & !_LC020 & _LC021;
-- Node name is 'lc'
-- Equation name is 'lc', location is LC027, type is output.
lc = LCELL( _EQ011 $ GND);
_EQ011 = !_LC018 & !_LC019 & _LC020 & !_LC021;
-- Node name is 'ld'
-- Equation name is 'ld', location is LC003, type is output.
ld = LCELL( _EQ012 $ GND);
_EQ012 = !_LC018 & _LC019 & _LC020 & _LC021
# !_LC018 & _LC019 & !_LC020 & !_LC021
# !_LC018 & !_LC019 & !_LC020 & _LC021;
-- Node name is 'le'
-- Equation name is 'le', location is LC004, type is output.
le = LCELL( _EQ013 $ !_LC018);
_EQ013 = _LC018 & !_LC019 & !_LC020 & _LC021
# !_LC018 & _LC020 & !_LC021
# !_LC018 & !_LC019 & !_LC021;
-- Node name is 'lf'
-- Equation name is 'lf', location is LC005, type is output.
lf = LCELL( _EQ014 $ !_LC018);
_EQ014 = !_LC018 & _LC019 & !_LC021
# !_LC018 & _LC019 & !_LC020
# !_LC018 & !_LC020 & !_LC021;
-- Node name is 'lg'
-- Equation name is 'lg', location is LC006, type is output.
lg = LCELL( _EQ015 $ GND);
_EQ015 = !_LC018 & _LC019 & _LC020 & _LC021
# !_LC018 & !_LC019 & !_LC020;
-- Node name is '|COUNT24:3|:20' = '|COUNT24:3|hq0'
-- Equation name is '_LC029', type is buried
_LC029 = TFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = en & !_LC008 & !_LC012 & _LC018 & !_LC019 & !_LC020 & _LC021 &
!_LC031;
-- Node name is '|COUNT24:3|:19' = '|COUNT24:3|hq1'
-- Equation name is '_LC031', type is buried
_LC031 = TFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = en & !_LC008 & !_LC012 & _LC018 & !_LC019 & !_LC020 & _LC021 &
_LC029 & !_LC031
# en & !_LC008 & !_LC012 & !_LC018 & !_LC019 & _LC020 & _LC021 &
!_LC029 & _LC031;
-- Node name is '|COUNT24:3|:18' = '|COUNT24:3|hq2'
-- Equation name is '_LC008', type is buried
_LC008 = TFFE( GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|COUNT24:3|:17' = '|COUNT24:3|hq3'
-- Equation name is '_LC012', type is buried
_LC012 = TFFE( GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|COUNT24:3|LPM_ADD_SUB:178|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC016', type is buried
_LC016 = LCELL( _LC019 $ _EQ018);
_EQ018 = _LC020 & _LC021;
-- Node name is '|COUNT24:3|LPM_ADD_SUB:178|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC013', type is buried
_LC013 = LCELL( _LC018 $ _EQ019);
_EQ019 = _LC019 & _LC020 & _LC021;
-- Node name is '|COUNT24:3|:16' = '|COUNT24:3|lq0'
-- Equation name is '_LC021', type is buried
_LC021 = TFFE( en, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|COUNT24:3|:15' = '|COUNT24:3|lq1'
-- Equation name is '_LC020', type is buried
_LC020 = TFFE(!_EQ020, GLOBAL( clk), VCC, VCC, VCC);
_EQ020 = !_LC008 & !_LC012 & _LC018 & !_LC019 & !_LC020 & _LC021 &
!_LC031
# !_LC021
# !en;
-- Node name is '|COUNT24:3|:14' = '|COUNT24:3|lq2'
-- Equation name is '_LC019', type is buried
_LC019 = DFFE( _EQ021 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ021 = !_LC008 & !_LC012 & !_LC018 & !_LC019 & _LC020 & _LC021 &
!_LC029 & _LC031
# !_LC008 & !_LC012 & _LC018 & !_LC019 & !_LC020 & _LC021 &
!_LC031
# en & !_LC016
# !en & !_LC019;
-- Node name is '|COUNT24:3|:13' = '|COUNT24:3|lq3'
-- Equation name is '_LC018', type is buried
_LC018 = DFFE( _EQ022 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ022 = !_LC008 & !_LC012 & !_LC018 & !_LC019 & _LC020 & _LC021 &
!_LC029 & _LC031
# en & !_LC008 & !_LC012 & _LC018 & !_LC019 & !_LC020 & _LC021 &
!_LC031
# en & !_LC013
# !en & !_LC018;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\top\mo24.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,292K
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