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📄 qiangda8.rpt

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_LC1_C14 = LCELL( _EQ059);
  _EQ059 = !_LC2_C24 & !_LC6_C24 & !_LC8_C14;

-- Node name is ':1356' 
-- Equation name is '_LC7_C13', type is buried 
_LC7_C13 = LCELL( _EQ060);
  _EQ060 =  _LC4_C13 & !_LC6_C13
         #  _LC1_C14 & !_LC2_C14 &  _LC4_C13
         #  _LC2_C14 & !_LC4_C13 &  _LC6_C13
         # !_LC1_C14 & !_LC4_C13 &  _LC6_C13;

-- Node name is ':1359' 
-- Equation name is '_LC8_C13', type is buried 
_LC8_C13 = LCELL( _EQ061);
  _EQ061 =  _LC1_C24 &  _LC4_C13
         # !_LC1_C24 &  _LC7_C13;

-- Node name is ':1368' 
-- Equation name is '_LC5_C13', type is buried 
_LC5_C13 = LCELL( _EQ062);
  _EQ062 =  _LC1_C24 &  _LC6_C13
         # !_LC1_C24 &  _LC2_C14 & !_LC6_C13
         #  _LC1_C14 & !_LC2_C14 &  _LC6_C13;

-- Node name is ':1374' 
-- Equation name is '_LC3_C14', type is buried 
_LC3_C14 = LCELL( _EQ063);
  _EQ063 = !_LC2_C24 & !_LC6_C13 &  _LC8_C14
         # !_LC6_C13 & !_LC6_C24 &  _LC8_C14
         #  _LC2_C24 & !_LC6_C13 &  _LC6_C24 & !_LC8_C14
         #  _LC2_C24 &  _LC6_C13 &  _LC8_C14
         #  _LC6_C13 &  _LC6_C24 &  _LC8_C14;

-- Node name is ':1377' 
-- Equation name is '_LC4_C14', type is buried 
_LC4_C14 = LCELL( _EQ064);
  _EQ064 =  _LC1_C24 &  _LC8_C14
         # !_LC1_C24 &  _LC3_C14;

-- Node name is ':1386' 
-- Equation name is '_LC2_C13', type is buried 
_LC2_C13 = LCELL( _EQ065);
  _EQ065 =  _LC1_C24 &  _LC2_C24
         #  _LC2_C24 &  _LC3_C13 & !_LC6_C24
         # !_LC1_C24 & !_LC2_C24 &  _LC3_C13 &  _LC6_C24
         #  _LC2_C24 & !_LC3_C13 &  _LC6_C24
         # !_LC1_C24 & !_LC2_C24 & !_LC3_C13 & !_LC6_C24;

-- Node name is ':1848' 
-- Equation name is '_LC6_B13', type is buried 
_LC6_B13 = LCELL( _EQ066);
  _EQ066 = !flag0 &  flag1 &  _LC6_C13
         #  flag0 &  flag1 &  _LC5_C24;

-- Node name is ':1855' 
-- Equation name is '_LC6_C14', type is buried 
_LC6_C14 = LCELL( _EQ067);
  _EQ067 =  flag0 & !flag1 &  _LC2_A22
         #  _LC5_C14;

-- Node name is ':1857' 
-- Equation name is '_LC5_C14', type is buried 
_LC5_C14 = LCELL( _EQ068);
  _EQ068 = !flag0 &  flag1 &  _LC8_C14
         # !flag0 & !flag1 &  _LC3_C24
         #  flag0 &  flag1 &  _LC3_C24;

-- Node name is ':1867' 
-- Equation name is '_LC8_B21', type is buried 
_LC8_B21 = LCELL( _EQ069);
  _EQ069 =  flag0 & !flag1 &  _LC3_A22
         #  _LC6_B21;

-- Node name is ':1869' 
-- Equation name is '_LC6_B21', type is buried 
_LC6_B21 = LCELL( _EQ070);
  _EQ070 = !flag0 &  flag1 &  _LC2_C24
         # !flag0 & !flag1 &  _LC4_C24
         #  flag0 &  flag1 &  _LC4_C24;

-- Node name is ':1879' 
-- Equation name is '_LC8_B13', type is buried 
_LC8_B13 = LCELL( _EQ071);
  _EQ071 =  flag0 & !flag1 &  _LC1_A22
         #  _LC7_B13;

-- Node name is ':1881' 
-- Equation name is '_LC7_B13', type is buried 
_LC7_B13 = LCELL( _EQ072);
  _EQ072 = !flag0 &  flag1 &  _LC6_C24
         # !flag0 & !flag1 &  _LC4_C13
         #  flag0 &  flag1 &  _LC4_C13;

-- Node name is ':2466' 
-- Equation name is '_LC5_B1', type is buried 
_LC5_B1  = LCELL( _EQ073);
  _EQ073 =  Disout0 & !Disout1 & !Disout2 &  Disout3;

-- Node name is ':2478' 
-- Equation name is '_LC8_B1', type is buried 
_LC8_B1  = LCELL( _EQ074);
  _EQ074 = !Disout0 & !Disout1 & !Disout2 &  Disout3;

-- Node name is ':2490' 
-- Equation name is '_LC5_B3', type is buried 
!_LC5_B3 = _LC5_B3~NOT;
_LC5_B3~NOT = LCELL( _EQ075);
  _EQ075 =  Disout3
         # !Disout2
         # !Disout1
         # !Disout0;

-- Node name is ':2526' 
-- Equation name is '_LC4_B1', type is buried 
!_LC4_B1 = _LC4_B1~NOT;
_LC4_B1~NOT = LCELL( _EQ076);
  _EQ076 =  Disout1
         #  Disout0
         #  Disout3
         # !Disout2;

-- Node name is ':2562' 
-- Equation name is '_LC3_B3', type is buried 
!_LC3_B3 = _LC3_B3~NOT;
_LC3_B3~NOT = LCELL( _EQ077);
  _EQ077 =  Disout1
         # !Disout0
         #  Disout3
         #  Disout2;

-- Node name is ':2574' 
-- Equation name is '_LC1_B3', type is buried 
_LC1_B3  = LCELL( _EQ078);
  _EQ078 = !Disout0 & !Disout1 & !Disout2 & !Disout3;

-- Node name is ':2579' 
-- Equation name is '_LC2_B5', type is buried 
_LC2_B5  = LCELL( _EQ079);
  _EQ079 =  Disout1 &  Disout3
         # !Disout0 &  Disout1
         #  Disout0 &  Disout3
         #  Disout1 & !Disout2
         # !Disout2 &  Disout3
         #  Disout0 & !Disout1 &  Disout2
         # !Disout1 &  Disout2 & !Disout3
         # !Disout0 &  Disout2 & !Disout3;

-- Node name is ':2625' 
-- Equation name is '_LC1_B4', type is buried 
_LC1_B4  = LCELL( _EQ080);
  _EQ080 =  Disout1 &  Disout3
         # !Disout0 & !Disout1
         # !Disout2 &  Disout3
         # !Disout0 &  Disout3
         # !Disout0 &  Disout2
         # !Disout1 &  Disout2 & !Disout3;

-- Node name is ':2667' 
-- Equation name is '_LC7_B3', type is buried 
_LC7_B3  = LCELL( _EQ081);
  _EQ081 =  Disout1 &  Disout3
         #  Disout2 &  Disout3
         # !Disout1 & !Disout2 & !Disout3
         # !Disout0 &  Disout1
         # !Disout0 &  Disout3
         # !Disout0 & !Disout2;

-- Node name is ':2673' 
-- Equation name is '_LC2_B3', type is buried 
_LC2_B3  = LCELL( _EQ082);
  _EQ082 = !_LC3_B3 &  _LC7_B3
         #  _LC1_B3;

-- Node name is '~2721~1' 
-- Equation name is '~2721~1', location is LC6_B1, type is buried.
-- synthesized logic cell 
_LC6_B1  = LCELL( _EQ083);
  _EQ083 = !Disout1 &  Disout2 &  Disout3
         #  Disout0 &  Disout1 & !Disout2 &  Disout3
         # !Disout0 &  Disout2 &  Disout3;

-- Node name is '~2721~2' 
-- Equation name is '~2721~2', location is LC3_B1, type is buried.
-- synthesized logic cell 
_LC3_B1  = LCELL( _EQ084);
  _EQ084 =  _LC5_B1
         #  _LC6_B1
         #  _LC8_B1;

-- Node name is '~2721~3' 
-- Equation name is '~2721~3', location is LC6_B3, type is buried.
-- synthesized logic cell 
_LC6_B3  = LCELL( _EQ085);
  _EQ085 = !_LC4_B1 &  _LC4_B3
         #  _LC3_B1 & !_LC4_B1 & !_LC5_B3;

-- Node name is ':2721' 
-- Equation name is '_LC8_B3', type is buried 
_LC8_B3  = LCELL( _EQ086);
  _EQ086 =  _LC1_B3
         #  _LC1_B5 & !_LC3_B3
         # !_LC3_B3 &  _LC6_B3;

-- Node name is '~2760~1' 
-- Equation name is '~2760~1', location is LC4_B3, type is buried.
-- synthesized logic cell 
_LC4_B3  = LCELL( _EQ087);
  _EQ087 =  Disout0 & !Disout1 &  Disout2 & !Disout3
         # !Disout0 &  Disout1 &  Disout2 & !Disout3;

-- Node name is ':2769' 
-- Equation name is '_LC2_B1', type is buried 
_LC2_B1  = LCELL( _EQ088);
  _EQ088 = !Disout1 & !Disout3
         #  Disout0 & !Disout3
         #  Disout0 & !Disout2
         #  Disout2 & !Disout3
         #  Disout0 & !Disout1
         # !Disout2 &  Disout3
         # !Disout1 & !Disout2;

-- Node name is ':2817' 
-- Equation name is '_LC1_B1', type is buried 
_LC1_B1  = LCELL( _EQ089);
  _EQ089 = !Disout0 & !Disout1 & !Disout3
         # !Disout2 & !Disout3
         #  Disout0 &  Disout1 & !Disout3
         #  Disout0 & !Disout1 &  Disout3
         # !Disout0 & !Disout2
         # !Disout1 & !Disout2;

-- Node name is '~2859~1' 
-- Equation name is '~2859~1', location is LC1_B5, type is buried.
-- synthesized logic cell 
_LC1_B5  = LCELL( _EQ090);
  _EQ090 =  Disout1 & !Disout2 & !Disout3;

-- Node name is ':2865' 
-- Equation name is '_LC7_B1', type is buried 
_LC7_B1  = LCELL( _EQ091);
  _EQ091 =  Disout1 &  Disout2
         #  Disout1 & !Disout3
         # !Disout0 &  Disout1
         # !Disout0 &  Disout3
         # !Disout0 & !Disout2
         # !Disout1 & !Disout2 &  Disout3
         #  Disout0 &  Disout2 & !Disout3;



Project Information                      d:\fthqj\eda\test5\test5\qiangda8.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,792K

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