📄 qiangda8.rpt
字号:
- 7 - B 21 DFFE 1 2 1 0 :10
- 5 - B 13 DFFE 1 2 1 0 :12
- 3 - B 21 DFFE 1 2 1 0 :14
- 1 - B 21 DFFE 1 2 1 0 :16
- 5 - C 24 DFFE 1 3 1 2 :29
- 3 - C 24 DFFE 1 3 1 2 :31
- 4 - C 24 DFFE 1 3 1 2 :33
- 4 - C 13 DFFE 1 3 1 4 :35
- 6 - C 13 DFFE 1 3 1 6 :37
- 8 - C 14 DFFE 1 3 1 6 :39
- 2 - C 24 DFFE 1 3 1 6 :41
- 6 - C 24 DFFE 1 3 1 5 :43
- 8 - C 24 DFFE 1 3 1 2 :47
- 2 - B 21 DFFE 1 1 0 15 flag1 (:59)
- 4 - B 21 DFFE 1 0 0 16 flag0 (:60)
- 4 - B 13 DFFE 1 4 0 15 Disout3 (:61)
- 7 - C 14 DFFE 1 4 0 15 Disout2 (:62)
- 5 - B 21 DFFE 1 4 0 15 Disout1 (:63)
- 2 - B 13 DFFE 1 4 0 14 Disout0 (:64)
- 2 - A 19 OR2 s 0 2 0 7 ~135~1
- 3 - A 24 OR2 3 1 0 1 :442
- 8 - A 24 AND2 2 1 0 1 :453
- 2 - A 24 OR2 2 1 0 1 :466
- 7 - A 24 OR2 3 1 0 1 :480
- 1 - A 19 OR2 3 1 0 1 :484
- 4 - A 24 OR2 s ! 4 0 0 2 ~501~1
- 6 - A 24 OR2 1 3 0 1 :501
- 6 - A 19 AND2 s 1 1 0 1 ~507~1
- 8 - A 19 AND2 s 3 1 0 2 ~507~2
- 5 - A 24 OR2 1 3 0 1 :507
- 7 - A 19 OR2 2 2 0 1 :513
- 1 - A 24 OR2 1 2 1 3 :534
- 5 - A 19 OR2 1 2 1 3 :540
- 4 - A 19 OR2 1 2 1 3 :546
- 3 - A 19 OR2 1 2 1 3 :552
- 6 - A 22 AND2 0 3 0 1 :635
- 4 - A 22 AND2 1 3 0 3 :705
- 4 - A 23 AND2 0 4 0 3 :717
- 8 - A 22 OR2 ! 0 4 0 2 :723
- 7 - A 23 OR2 ! 0 4 0 2 :750
- 8 - A 23 AND2 s 0 4 0 1 ~775~1
- 3 - A 23 AND2 0 3 0 1 :775
- 2 - A 22 OR2 0 3 1 13 :878
- 5 - A 22 OR2 s 1 3 0 2 ~880~1
- 7 - A 22 OR2 s 0 4 0 1 ~885~1
- 3 - A 22 OR2 1 3 1 13 :887
- 1 - A 22 OR2 0 3 1 13 :896
- 5 - A 23 OR2 ! 0 2 0 1 :909
- 1 - A 23 OR2 0 3 1 11 :987
- 7 - A 13 OR2 0 3 1 11 :1005
- 3 - B 13 OR2 0 4 1 1 :1057
- 2 - A 23 OR2 0 4 1 1 :1063
- 6 - A 23 OR2 0 4 1 1 :1069
- 1 - B 13 OR2 0 4 1 1 :1075
- 7 - C 24 AND2 0 2 0 4 :1129
- 1 - C 24 OR2 0 4 0 6 :1167
- 1 - C 13 OR2 0 4 0 1 :1179
- 3 - C 13 OR2 0 2 0 1 :1216
- 1 - C 14 AND2 0 3 0 3 :1218
- 7 - C 13 OR2 0 4 0 1 :1356
- 8 - C 13 OR2 0 3 0 1 :1359
- 5 - C 13 OR2 0 4 0 1 :1368
- 3 - C 14 OR2 0 4 0 1 :1374
- 4 - C 14 OR2 0 3 0 1 :1377
- 2 - C 13 OR2 0 4 0 1 :1386
- 6 - B 13 OR2 0 4 0 1 :1848
- 6 - C 14 OR2 0 4 0 1 :1855
- 5 - C 14 OR2 0 4 0 1 :1857
- 8 - B 21 OR2 0 4 0 1 :1867
- 6 - B 21 OR2 0 4 0 1 :1869
- 8 - B 13 OR2 0 4 0 1 :1879
- 7 - B 13 OR2 0 4 0 1 :1881
- 5 - B 01 AND2 0 4 0 1 :2466
- 8 - B 01 AND2 0 4 0 1 :2478
- 5 - B 03 OR2 ! 0 4 0 1 :2490
- 4 - B 01 OR2 ! 0 4 0 1 :2526
- 3 - B 03 OR2 ! 0 4 0 2 :2562
- 1 - B 03 AND2 0 4 0 2 :2574
- 2 - B 05 OR2 0 4 1 0 :2579
- 1 - B 04 OR2 0 4 1 0 :2625
- 7 - B 03 OR2 0 4 0 1 :2667
- 2 - B 03 OR2 0 3 1 0 :2673
- 6 - B 01 OR2 s 0 4 0 1 ~2721~1
- 3 - B 01 OR2 s 0 3 0 1 ~2721~2
- 6 - B 03 OR2 s 0 4 0 1 ~2721~3
- 8 - B 03 OR2 0 4 1 0 :2721
- 4 - B 03 OR2 s 0 4 0 1 ~2760~1
- 2 - B 01 OR2 0 4 1 0 :2769
- 1 - B 01 OR2 0 4 1 0 :2817
- 1 - B 05 AND2 s 0 3 0 1 ~2859~1
- 7 - B 01 OR2 0 4 1 0 :2865
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\fthqj\eda\test5\test5\qiangda8.rpt
qiangda8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 11/ 96( 11%) 0/ 48( 0%) 21/ 48( 43%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 10/ 96( 10%) 3/ 48( 6%) 15/ 48( 31%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 15/ 48( 31%) 2/16( 12%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 6/24( 25%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\fthqj\eda\test5\test5\qiangda8.rpt
qiangda8
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 disClk
INPUT 9 CLK
Device-Specific Information: d:\fthqj\eda\test5\test5\qiangda8.rpt
qiangda8
** EQUATIONS **
CLK : INPUT;
disClk : INPUT;
Players0 : INPUT;
Players1 : INPUT;
Players2 : INPUT;
Players3 : INPUT;
Players4 : INPUT;
Players5 : INPUT;
Players6 : INPUT;
Players7 : INPUT;
Reset : INPUT;
Start : INPUT;
-- Node name is 'CurPlayer0'
-- Equation name is 'CurPlayer0', type is output
CurPlayer0 = _LC3_A19;
-- Node name is 'CurPlayer1'
-- Equation name is 'CurPlayer1', type is output
CurPlayer1 = _LC4_A19;
-- Node name is 'CurPlayer2'
-- Equation name is 'CurPlayer2', type is output
CurPlayer2 = _LC5_A19;
-- Node name is 'CurPlayer3'
-- Equation name is 'CurPlayer3', type is output
CurPlayer3 = _LC1_A24;
-- Node name is 'DisLed0'
-- Equation name is 'DisLed0', type is output
DisLed0 = _LC7_B1;
-- Node name is 'DisLed1'
-- Equation name is 'DisLed1', type is output
DisLed1 = _LC1_B1;
-- Node name is 'DisLed2'
-- Equation name is 'DisLed2', type is output
DisLed2 = _LC2_B1;
-- Node name is 'DisLed3'
-- Equation name is 'DisLed3', type is output
DisLed3 = _LC8_B3;
-- Node name is 'DisLed4'
-- Equation name is 'DisLed4', type is output
DisLed4 = _LC2_B3;
-- Node name is 'DisLed5'
-- Equation name is 'DisLed5', type is output
DisLed5 = _LC1_B4;
-- Node name is 'DisLed6'
-- Equation name is 'DisLed6', type is output
DisLed6 = _LC2_B5;
-- Node name is ':64' = 'Disout0'
-- Equation name is 'Disout0', location is LC2_B13, type is buried.
Disout0 = DFFE( _EQ001, disClk, VCC, VCC, VCC);
_EQ001 = !flag0 & !flag1 & _LC1_B13
# flag1 & _LC8_B13
# flag0 & _LC8_B13;
-- Node name is ':63' = 'Disout1'
-- Equation name is 'Disout1', location is LC5_B21, type is buried.
Disout1 = DFFE( _EQ002, disClk, VCC, VCC, VCC);
_EQ002 = !flag0 & !flag1 & _LC6_A23
# flag1 & _LC8_B21
# flag0 & _LC8_B21;
-- Node name is ':62' = 'Disout2'
-- Equation name is 'Disout2', location is LC7_C14, type is buried.
Disout2 = DFFE( _EQ003, disClk, VCC, VCC, VCC);
_EQ003 = flag1 & _LC6_C14
# flag0 & _LC6_C14
# !flag0 & !flag1 & _LC2_A23;
-- Node name is ':61' = 'Disout3'
-- Equation name is 'Disout3', location is LC4_B13, type is buried.
Disout3 = DFFE( _EQ004, disClk, VCC, VCC, VCC);
_EQ004 = !flag0 & !flag1 & _LC3_B13
# _LC6_B13;
-- Node name is 'DisPlayer0'
-- Equation name is 'DisPlayer0', type is output
DisPlayer0 = _LC1_B13;
-- Node name is 'DisPlayer1'
-- Equation name is 'DisPlayer1', type is output
DisPlayer1 = _LC6_A23;
-- Node name is 'DisPlayer2'
-- Equation name is 'DisPlayer2', type is output
DisPlayer2 = _LC2_A23;
-- Node name is 'DisPlayer3'
-- Equation name is 'DisPlayer3', type is output
DisPlayer3 = _LC3_B13;
-- Node name is 'DisSelect0'
-- Equation name is 'DisSelect0', type is output
DisSelect0 = _LC1_B21;
-- Node name is 'DisSelect1'
-- Equation name is 'DisSelect1', type is output
DisSelect1 = _LC3_B21;
-- Node name is 'DisSelect2'
-- Equation name is 'DisSelect2', type is output
DisSelect2 = _LC5_B13;
-- Node name is 'DisSelect3'
-- Equation name is 'DisSelect3', type is output
DisSelect3 = _LC7_B21;
-- Node name is ':60' = 'flag0'
-- Equation name is 'flag0', location is LC4_B21, type is buried.
flag0 = DFFE(!flag0, disClk, VCC, VCC, VCC);
-- Node name is ':59' = 'flag1'
-- Equation name is 'flag1', location is LC2_B21, type is buried.
flag1 = DFFE( _EQ005, disClk, VCC, VCC, VCC);
_EQ005 = !flag0 & flag1
# flag0 & !flag1;
-- Node name is 'status0'
-- Equation name is 'status0', type is output
status0 = _LC1_A22;
-- Node name is 'status1'
-- Equation name is 'status1', type is output
status1 = _LC3_A22;
-- Node name is 'status2'
-- Equation name is 'status2', type is output
status2 = _LC2_A22;
-- Node name is 'TimeOut'
-- Equation name is 'TimeOut', type is output
TimeOut = _LC8_C24;
-- Node name is 'timeRecord0'
-- Equation name is 'timeRecord0', type is output
timeRecord0 = _LC6_C24;
-- Node name is 'timeRecord1'
-- Equation name is 'timeRecord1', type is output
timeRecord1 = _LC2_C24;
-- Node name is 'timeRecord2'
-- Equation name is 'timeRecord2', type is output
timeRecord2 = _LC8_C14;
-- Node name is 'timeRecord3'
-- Equation name is 'timeRecord3', type is output
timeRecord3 = _LC6_C13;
-- Node name is 'timeRecord4'
-- Equation name is 'timeRecord4', type is output
timeRecord4 = _LC4_C13;
-- Node name is 'timeRecord5'
-- Equation name is 'timeRecord5', type is output
timeRecord5 = _LC4_C24;
-- Node name is 'timeRecord6'
-- Equation name is 'timeRecord6', type is output
timeRecord6 = _LC3_C24;
-- Node name is 'timeRecord7'
-- Equation name is 'timeRecord7', type is output
timeRecord7 = _LC5_C24;
-- Node name is 'TimerEnable0'
-- Equation name is 'TimerEnable0', type is output
TimerEnable0 = _LC7_A13;
-- Node name is 'TimerEnable1'
-- Equation name is 'TimerEnable1', type is output
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