📄 qiangda8.rpt
字号:
Project Information d:\fthqj\eda\test5\test5\qiangda8.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 06/11/2008 18:29:41
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
QIANGDA8
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
qiangda8 EPF10K10LC84-4 12 33 0 0 0 % 92 15 %
User Pins: 12 33 0
Project Information d:\fthqj\eda\test5\test5\qiangda8.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
qiangda8@29 CLK
qiangda8@30 disClk
qiangda8@11 DisLed0
qiangda8@10 DisLed1
qiangda8@9 DisLed2
qiangda8@8 DisLed3
qiangda8@7 DisLed4
qiangda8@6 DisLed5
qiangda8@5 DisLed6
qiangda8@67 DisSelect0
qiangda8@66 DisSelect1
qiangda8@65 DisSelect2
qiangda8@64 DisSelect3
qiangda8@39 Players0
qiangda8@47 Players1
qiangda8@48 Players2
qiangda8@49 Players3
qiangda8@50 Players4
qiangda8@51 Players5
qiangda8@52 Players6
qiangda8@53 Players7
qiangda8@35 Reset
qiangda8@36 Start
Project Information d:\fthqj\eda\test5\test5\qiangda8.rpt
** FILE HIERARCHY **
|lpm_add_sub:1259|
|lpm_add_sub:1259|addcore:adder|
|lpm_add_sub:1259|altshift:result_ext_latency_ffs|
|lpm_add_sub:1259|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1259|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1300|
|lpm_add_sub:1300|addcore:adder|
|lpm_add_sub:1300|altshift:result_ext_latency_ffs|
|lpm_add_sub:1300|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1300|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\fthqj\eda\test5\test5\qiangda8.rpt
qiangda8
***** Logic for device 'qiangda8' compiled without errors.
Device: EPF10K10LC84-4
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
T
t i t t
i m i i ^
m e m m C
R e r e e O
D D D D D D D E R s E R R N
i i i i i i i V S G G G e G t n e e F
s s s s s s s C E N N N c N a a c c _ ^
L L L L L L L C R D D D o D t b o o # D n
e e e e e e e I V I I I r I u l r r T O C
d d d d d d d N E N N N d N s e d d C N E
0 1 2 3 4 5 6 T D T T T 3 T 0 1 5 7 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | CurPlayer3
^nCE | 14 72 | CurPlayer0
#TDI | 15 71 | CurPlayer1
RESERVED | 16 70 | CurPlayer2
DisPlayer3 | 17 69 | TimeOut
RESERVED | 18 68 | GNDINT
TimerEnable0 | 19 67 | DisSelect0
VCCINT | 20 66 | DisSelect1
DisPlayer0 | 21 65 | DisSelect2
DisPlayer2 | 22 EPF10K10LC84-4 64 | DisSelect3
timeRecord4 | 23 63 | VCCINT
DisPlayer1 | 24 62 | RESERVED
RESERVED | 25 61 | timeRecord1
GNDINT | 26 60 | timeRecord6
RESERVED | 27 59 | timeRecord2
status2 | 28 58 | timeRecord0
CLK | 29 57 | #TMS
disClk | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | status1
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R S R R P V G G G G V G P P P P P P P
C n e t E E l C N N N N C N l l l l l l l
C C s a S S a C D D D D C D a a a a a a a
I O e r E E y I I I I I I I y y y y y y y
N N t t R R e N N N N N N N e e e e e e e
T F V V r T T T T T T T r r r r r r r
I E E s s s s s s s s
G D D 0 1 2 3 4 5 6 7
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\fthqj\eda\test5\test5\qiangda8.rpt
qiangda8
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A13 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A19 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
A22 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 5/22( 22%)
A23 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
A24 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
B1 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
B3 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 7/22( 31%)
B4 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
B5 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B13 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 12/22( 54%)
B21 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 1/2 0/2 5/22( 22%)
C13 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
C14 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 13/22( 59%)
C24 8/ 8(100%) 6/ 8( 75%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 45/53 ( 84%)
Total logic cells used: 92/576 ( 15%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.63/4 ( 90%)
Total fan-in: 334/2304 ( 14%)
Total input pins required: 12
Total input I/O cell registers required: 0
Total output pins required: 33
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 92
Total flipflops required: 19
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 12/ 576 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 8 0 0 8 8 8 33/0
B: 8 0 8 1 2 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 8 0 0 0 35/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 0 0 0 0 0 0 0 0 8 24/0
Total: 8 0 8 1 2 0 0 0 0 0 0 0 0 17 8 0 0 0 0 8 0 8 8 8 16 92/0
Device-Specific Information: d:\fthqj\eda\test5\test5\qiangda8.rpt
qiangda8
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
29 - - C -- INPUT 0 0 0 9 CLK
30 - - C -- INPUT 0 0 0 10 disClk
39 - - - 11 INPUT 0 0 0 3 Players0
47 - - - 14 INPUT 0 0 0 3 Players1
48 - - - 15 INPUT 0 0 0 3 Players2
49 - - - 16 INPUT 0 0 0 3 Players3
50 - - - 17 INPUT 0 0 0 3 Players4
51 - - - 18 INPUT 0 0 0 3 Players5
52 - - - 19 INPUT 0 0 0 3 Players6
53 - - - 20 INPUT 0 0 0 4 Players7
35 - - - 06 INPUT 0 0 0 6 Reset
36 - - - 07 INPUT 0 0 0 1 Start
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\fthqj\eda\test5\test5\qiangda8.rpt
qiangda8
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
72 - - A -- OUTPUT 0 1 0 0 CurPlayer0
71 - - A -- OUTPUT 0 1 0 0 CurPlayer1
70 - - A -- OUTPUT 0 1 0 0 CurPlayer2
73 - - A -- OUTPUT 0 1 0 0 CurPlayer3
11 - - - 01 OUTPUT 0 1 0 0 DisLed0
10 - - - 01 OUTPUT 0 1 0 0 DisLed1
9 - - - 02 OUTPUT 0 1 0 0 DisLed2
8 - - - 03 OUTPUT 0 1 0 0 DisLed3
7 - - - 03 OUTPUT 0 1 0 0 DisLed4
6 - - - 04 OUTPUT 0 1 0 0 DisLed5
5 - - - 05 OUTPUT 0 1 0 0 DisLed6
21 - - B -- OUTPUT 0 1 0 0 DisPlayer0
24 - - B -- OUTPUT 0 1 0 0 DisPlayer1
22 - - B -- OUTPUT 0 1 0 0 DisPlayer2
17 - - A -- OUTPUT 0 1 0 0 DisPlayer3
67 - - B -- OUTPUT 0 1 0 0 DisSelect0
66 - - B -- OUTPUT 0 1 0 0 DisSelect1
65 - - B -- OUTPUT 0 1 0 0 DisSelect2
64 - - B -- OUTPUT 0 1 0 0 DisSelect3
81 - - - 22 OUTPUT 0 1 0 0 status0
54 - - - 21 OUTPUT 0 1 0 0 status1
28 - - C -- OUTPUT 0 1 0 0 status2
69 - - A -- OUTPUT 0 1 0 0 TimeOut
58 - - C -- OUTPUT 0 1 0 0 timeRecord0
61 - - C -- OUTPUT 0 1 0 0 timeRecord1
59 - - C -- OUTPUT 0 1 0 0 timeRecord2
83 - - - 13 OUTPUT 0 1 0 0 timeRecord3
23 - - B -- OUTPUT 0 1 0 0 timeRecord4
79 - - - 24 OUTPUT 0 1 0 0 timeRecord5
60 - - C -- OUTPUT 0 1 0 0 timeRecord6
78 - - - 24 OUTPUT 0 1 0 0 timeRecord7
19 - - A -- OUTPUT 0 1 0 0 TimerEnable0
80 - - - 23 OUTPUT 0 1 0 0 TimerEnable1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\fthqj\eda\test5\test5\qiangda8.rpt
qiangda8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 14 AND2 0 3 0 2 |LPM_ADD_SUB:1259|addcore:adder|:125
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -