cora.tan.qmsg

8*8的点阵设计例子可以让刚开始做设计的朋友来参考一下

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 03 16:13:49 2008 " "Info: Processing started: Thu Jan 03 16:13:49 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off cora -c cora --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cora -c cora --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "sel\[1\] lie\[4\] 14.750 ns Longest " "Info: Longest tpd from source pin \"sel\[1\]\" to destination pin \"lie\[4\]\" is 14.750 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sel\[1\] 1 PIN PIN_28 11 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 11; PIN Node = 'sel\[1\]'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "" { sel[1] } "NODE_NAME" } } { "cora.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/cora.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.502 ns) + CELL(0.114 ns) 9.085 ns Mux20~230 2 COMB LC_X32_Y4_N5 2 " "Info: 2: + IC(7.502 ns) + CELL(0.114 ns) = 9.085 ns; Loc. = LC_X32_Y4_N5; Fanout = 2; COMB Node = 'Mux20~230'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "7.616 ns" { sel[1] Mux20~230 } "NODE_NAME" } } { "cora.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/cora.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.442 ns) 9.942 ns Mux18~105 3 COMB LC_X32_Y4_N4 2 " "Info: 3: + IC(0.415 ns) + CELL(0.442 ns) = 9.942 ns; Loc. = LC_X32_Y4_N4; Fanout = 2; COMB Node = 'Mux18~105'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "0.857 ns" { Mux20~230 Mux18~105 } "NODE_NAME" } } { "cora.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/cora.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.108 ns) 14.750 ns lie\[4\] 4 PIN PIN_112 0 " "Info: 4: + IC(2.700 ns) + CELL(2.108 ns) = 14.750 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'lie\[4\]'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.808 ns" { Mux18~105 lie[4] } "NODE_NAME" } } { "cora.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/cora.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.133 ns ( 28.02 % ) " "Info: Total cell delay = 4.133 ns ( 28.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.617 ns ( 71.98 % ) " "Info: Total interconnect delay = 10.617 ns ( 71.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "14.750 ns" { sel[1] Mux20~230 Mux18~105 lie[4] } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "14.750 ns" { sel[1] sel[1]~out0 Mux20~230 Mux18~105 lie[4] } { 0.000ns 0.000ns 7.502ns 0.415ns 2.700ns } { 0.000ns 1.469ns 0.114ns 0.442ns 2.108ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 03 16:13:49 2008 " "Info: Processing ended: Thu Jan 03 16:13:49 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}