dianzhen.hier_info

8*8的点阵设计例子可以让刚开始做设计的朋友来参考一下

|dianzhen
hang[0] <= cora:inst2.hang[0]
hang[1] <= cora:inst2.hang[1]
hang[2] <= cora:inst2.hang[2]
hang[3] <= cora:inst2.hang[3]
hang[4] <= cora:inst2.hang[4]
hang[5] <= cora:inst2.hang[5]
hang[6] <= cora:inst2.hang[6]
hang[7] <= cora:inst2.hang[7]
40MHz => fengpin:inst3.40MHz
lie[0] <= cora:inst2.lie[0]
lie[1] <= cora:inst2.lie[1]
lie[2] <= cora:inst2.lie[2]
lie[3] <= cora:inst2.lie[3]
lie[4] <= cora:inst2.lie[4]
lie[5] <= cora:inst2.lie[5]
lie[6] <= cora:inst2.lie[6]
lie[7] <= cora:inst2.lie[7]


|dianzhen|cora:inst2
ch[0] => Mux14.IN5
ch[0] => Mux15.IN5
ch[0] => Mux16.IN5
ch[0] => Mux17.IN5
ch[0] => Mux18.IN5
ch[0] => Mux19.IN5
ch[0] => Mux20.IN5
ch[0] => Mux21.IN5
ch[1] => Mux14.IN4
ch[1] => Mux15.IN4
ch[1] => Mux16.IN4
ch[1] => Mux17.IN4
ch[1] => Mux18.IN4
ch[1] => Mux19.IN4
ch[1] => Mux20.IN4
ch[1] => Mux21.IN4
sel[0] => Mux0.IN10
sel[0] => Mux1.IN10
sel[0] => Mux2.IN10
sel[0] => Mux4.IN10
sel[0] => Mux5.IN10
sel[0] => Mux6.IN10
sel[0] => Mux7.IN10
sel[0] => Mux8.IN10
sel[0] => Mux9.IN10
sel[0] => Mux10.IN10
sel[0] => Mux11.IN10
sel[0] => Mux12.IN10
sel[0] => Mux13.IN10
sel[1] => Mux0.IN9
sel[1] => Mux1.IN9
sel[1] => Mux2.IN9
sel[1] => Mux3.IN5
sel[1] => Mux4.IN9
sel[1] => Mux5.IN9
sel[1] => Mux6.IN9
sel[1] => Mux7.IN9
sel[1] => Mux8.IN9
sel[1] => Mux9.IN9
sel[1] => Mux10.IN9
sel[1] => Mux11.IN9
sel[1] => Mux12.IN9
sel[1] => Mux13.IN9
sel[2] => Mux0.IN8
sel[2] => Mux1.IN8
sel[2] => Mux2.IN8
sel[2] => Mux3.IN4
sel[2] => Mux4.IN8
sel[2] => Mux5.IN8
sel[2] => Mux6.IN8
sel[2] => Mux7.IN8
sel[2] => Mux8.IN8
sel[2] => Mux9.IN8
sel[2] => Mux10.IN8
sel[2] => Mux11.IN8
sel[2] => Mux12.IN8
sel[2] => Mux13.IN8
hang[0] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE
hang[1] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE
hang[2] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE
hang[3] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE
hang[4] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE
hang[5] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
hang[6] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
hang[7] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
lie[0] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE
lie[1] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE
lie[2] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE
lie[3] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE
lie[4] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE
lie[5] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE
lie[6] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE
lie[7] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE


|dianzhen|chw:inst
clk => tmp[0].CLK
clk => tmp[1].CLK
clk => cnt[0].CLK
clk => cnt[1].CLK
clk => cnt[2].CLK
clk => cnt[3].CLK
clk => cnt[4].CLK
clk => cnt[5].CLK
clk => cnt[6].CLK
clk => cnt[7].CLK
clk => cnt[8].CLK
clk => cnt[9].CLK
clk => cnt[10].CLK
clk => cnt[11].CLK
clk => cnt[12].CLK
clk => cnt[13].CLK
clk => cnt[14].CLK
clk => cnt[15].CLK
clk => cnt[16].CLK
clk => cnt[17].CLK
clk => cnt[18].CLK
clk => cnt[19].CLK
clk => cnt[20].CLK
clk => cnt[21].CLK
clk => cnt[22].CLK
clk => cnt[23].CLK
clk => cnt[24].CLK
clk => cnt[25].CLK
clk => cnt[26].CLK
clk => cnt[27].CLK
clk => cnt[28].CLK
clk => cnt[29].CLK
clk => cnt[30].CLK
clk => cnt[31].CLK
q[0] <= tmp[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= tmp[1].DB_MAX_OUTPUT_PORT_TYPE


|dianzhen|fengpin:inst3
400Hz <= 74160:inst4.RCO
40MHz => 74160:inst.CLK


|dianzhen|fengpin:inst3|74160:inst4
RCO <= 45.DB_MAX_OUTPUT_PORT_TYPE
ENT => 45.IN0
ENT => 47.IN0
ENT => 65.IN0
CLRN => 6.ACLR
CLRN => 9.ACLR
CLRN => 8.ACLR
CLRN => 7.ACLR
CLK => 6.CLK
CLK => 9.CLK
CLK => 8.CLK
CLK => 7.CLK
LDN => 32.IN0
LDN => 47.IN2
LDN => 33.IN0
LDN => 49.IN1
LDN => 27.IN0
LDN => 30.IN0
ENP => 47.IN1
ENP => 65.IN1
A => 31.IN0
D => 24.IN0
C => 26.IN0
B => 29.IN0
QD <= 9.DB_MAX_OUTPUT_PORT_TYPE
QC <= 8.DB_MAX_OUTPUT_PORT_TYPE
QB <= 7.DB_MAX_OUTPUT_PORT_TYPE
QA <= 6.DB_MAX_OUTPUT_PORT_TYPE


|dianzhen|fengpin:inst3|74160:inst3
RCO <= 45.DB_MAX_OUTPUT_PORT_TYPE
ENT => 45.IN0
ENT => 47.IN0
ENT => 65.IN0
CLRN => 6.ACLR
CLRN => 9.ACLR
CLRN => 8.ACLR
CLRN => 7.ACLR
CLK => 6.CLK
CLK => 9.CLK
CLK => 8.CLK
CLK => 7.CLK
LDN => 32.IN0
LDN => 47.IN2
LDN => 33.IN0
LDN => 49.IN1
LDN => 27.IN0
LDN => 30.IN0
ENP => 47.IN1
ENP => 65.IN1
A => 31.IN0
D => 24.IN0
C => 26.IN0
B => 29.IN0
QD <= 9.DB_MAX_OUTPUT_PORT_TYPE
QC <= 8.DB_MAX_OUTPUT_PORT_TYPE
QB <= 7.DB_MAX_OUTPUT_PORT_TYPE
QA <= 6.DB_MAX_OUTPUT_PORT_TYPE


|dianzhen|fengpin:inst3|74160:inst2
RCO <= 45.DB_MAX_OUTPUT_PORT_TYPE
ENT => 45.IN0
ENT => 47.IN0
ENT => 65.IN0
CLRN => 6.ACLR
CLRN => 9.ACLR
CLRN => 8.ACLR
CLRN => 7.ACLR
CLK => 6.CLK
CLK => 9.CLK
CLK => 8.CLK
CLK => 7.CLK
LDN => 32.IN0
LDN => 47.IN2
LDN => 33.IN0
LDN => 49.IN1
LDN => 27.IN0
LDN => 30.IN0
ENP => 47.IN1
ENP => 65.IN1
A => 31.IN0
D => 24.IN0
C => 26.IN0
B => 29.IN0
QD <= 9.DB_MAX_OUTPUT_PORT_TYPE
QC <= 8.DB_MAX_OUTPUT_PORT_TYPE
QB <= 7.DB_MAX_OUTPUT_PORT_TYPE
QA <= 6.DB_MAX_OUTPUT_PORT_TYPE


|dianzhen|fengpin:inst3|74160:inst1
RCO <= 45.DB_MAX_OUTPUT_PORT_TYPE
ENT => 45.IN0
ENT => 47.IN0
ENT => 65.IN0
CLRN => 6.ACLR
CLRN => 9.ACLR
CLRN => 8.ACLR
CLRN => 7.ACLR
CLK => 6.CLK
CLK => 9.CLK
CLK => 8.CLK
CLK => 7.CLK
LDN => 32.IN0
LDN => 47.IN2
LDN => 33.IN0
LDN => 49.IN1
LDN => 27.IN0
LDN => 30.IN0
ENP => 47.IN1
ENP => 65.IN1
A => 31.IN0
D => 24.IN0
C => 26.IN0
B => 29.IN0
QD <= 9.DB_MAX_OUTPUT_PORT_TYPE
QC <= 8.DB_MAX_OUTPUT_PORT_TYPE
QB <= 7.DB_MAX_OUTPUT_PORT_TYPE
QA <= 6.DB_MAX_OUTPUT_PORT_TYPE


|dianzhen|fengpin:inst3|74160:inst
RCO <= 45.DB_MAX_OUTPUT_PORT_TYPE
ENT => 45.IN0
ENT => 47.IN0
ENT => 65.IN0
CLRN => 6.ACLR
CLRN => 9.ACLR
CLRN => 8.ACLR
CLRN => 7.ACLR
CLK => 6.CLK
CLK => 9.CLK
CLK => 8.CLK
CLK => 7.CLK
LDN => 32.IN0
LDN => 47.IN2
LDN => 33.IN0
LDN => 49.IN1
LDN => 27.IN0
LDN => 30.IN0
ENP => 47.IN1
ENP => 65.IN1
A => 31.IN0
D => 24.IN0
C => 26.IN0
B => 29.IN0
QD <= 9.DB_MAX_OUTPUT_PORT_TYPE
QC <= 8.DB_MAX_OUTPUT_PORT_TYPE
QB <= 7.DB_MAX_OUTPUT_PORT_TYPE
QA <= 6.DB_MAX_OUTPUT_PORT_TYPE


|dianzhen|cnta:inst1
clk => tmp[0].CLK
clk => tmp[1].CLK
clk => tmp[2].CLK
q[0] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= Add1.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= Add1.DB_MAX_OUTPUT_PORT_TYPE