fengpin.tan.rpt

8*8的点阵设计例子可以让刚开始做设计的朋友来参考一下

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|6 ; 74160:inst2|6 ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.064 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|8 ; 74160:inst1|9 ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.265 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|8 ; 74160:inst1|8 ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.261 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|8 ; 74160:inst2|9 ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.029 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|8 ; 74160:inst2|8 ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.028 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst|8  ; 74160:inst|9  ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.274 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst|8  ; 74160:inst|8  ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.273 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst|7  ; 74160:inst|8  ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.240 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|9 ; 74160:inst2|7 ; 40MHz      ; 40MHz    ; None                        ; None                      ; 0.854 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|9 ; 74160:inst2|9 ; 40MHz      ; 40MHz    ; None                        ; None                      ; 0.852 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|6 ; 74160:inst1|7 ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.068 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|6 ; 74160:inst1|6 ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.062 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst|7  ; 74160:inst|9  ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.145 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst|7  ; 74160:inst|7  ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.138 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst|9  ; 74160:inst|7  ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.044 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst|9  ; 74160:inst|9  ; 40MHz      ; 40MHz    ; None                        ; None                      ; 1.040 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|9 ; 74160:inst1|7 ; 40MHz      ; 40MHz    ; None                        ; None                      ; 0.855 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|9 ; 74160:inst1|9 ; 40MHz      ; 40MHz    ; None                        ; None                      ; 0.853 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst|6  ; 74160:inst|7  ; 40MHz      ; 40MHz    ; None                        ; None                      ; 0.919 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst|6  ; 74160:inst|8  ; 40MHz      ; 40MHz    ; None                        ; None                      ; 0.913 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst|6  ; 74160:inst|9  ; 40MHz      ; 40MHz    ; None                        ; None                      ; 0.910 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst|6  ; 74160:inst|6  ; 40MHz      ; 40MHz    ; None                        ; None                      ; 0.903 ns                ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------------+
; tco                                                                    ;
+-------+--------------+------------+---------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From          ; To    ; From Clock ;
+-------+--------------+------------+---------------+-------+------------+
; N/A   ; None         ; 29.398 ns  ; 74160:inst4|6 ; 400Hz ; 40MHz      ;
; N/A   ; None         ; 29.245 ns  ; 74160:inst4|9 ; 400Hz ; 40MHz      ;
+-------+--------------+------------+---------------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jan 03 16:25:01 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fengpin -c fengpin --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "40MHz" is an undefined clock
Warning: Found 12 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "74160:inst|6" as buffer
    Info: Detected ripple clock "74160:inst|9" as buffer
    Info: Detected gated clock "74160:inst|49~26" as buffer
    Info: Detected ripple clock "74160:inst1|9" as buffer
    Info: Detected ripple clock "74160:inst1|6" as buffer
    Info: Detected gated clock "74160:inst1|49~26" as buffer
    Info: Detected ripple clock "74160:inst2|9" as buffer
    Info: Detected ripple clock "74160:inst2|6" as buffer
    Info: Detected gated clock "74160:inst2|49~26" as buffer
    Info: Detected ripple clock "74160:inst3|9" as buffer
    Info: Detected ripple clock "74160:inst3|6" as buffer
    Info: Detected gated clock "74160:inst3|49~26" as buffer
Info: Clock "40MHz" Internal fmax is restricted to 275.03 MHz between source register "74160:inst4|9" and destination register "74160:inst4|7"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N9; Fanout = 3; REG Node = '74160:inst4|9'
            Info: 2: + IC(0.562 ns) + CELL(0.738 ns) = 1.300 ns; Loc. = LC_X1_Y2_N2; Fanout = 3; REG Node = '74160:inst4|7'
            Info: Total cell delay = 0.738 ns ( 56.77 % )
            Info: Total interconnect delay = 0.562 ns ( 43.23 % )
        Info: - Smallest clock skew is -0.904 ns
            Info: + Shortest clock path from clock "40MHz" to destination register is 24.033 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = '40MHz'
                Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N5; Fanout = 5; REG Node = '74160:inst|6'
                Info: 3: + IC(0.608 ns) + CELL(0.114 ns) = 3.888 ns; Loc. = LC_X27_Y10_N2; Fanout = 4; COMB Node = '74160:inst|49~26'
                Info: 4: + IC(3.429 ns) + CELL(0.935 ns) = 8.252 ns; Loc. = LC_X7_Y9_N3; Fanout = 3; REG Node = '74160:inst1|9'
                Info: 5: + IC(0.545 ns) + CELL(0.114 ns) = 8.911 ns; Loc. = LC_X7_Y9_N0; Fanout = 4; COMB Node = '74160:inst1|49~26'
                Info: 6: + IC(3.966 ns) + CELL(0.935 ns) = 13.812 ns; Loc. = LC_X8_Y10_N6; Fanout = 3; REG Node = '74160:inst2|9'
                Info: 7: + IC(0.549 ns) + CELL(0.114 ns) = 14.475 ns; Loc. = LC_X8_Y10_N2; Fanout = 4; COMB Node = '74160:inst2|49~26'
                Info: 8: + IC(3.463 ns) + CELL(0.935 ns) = 18.873 ns; Loc. = LC_X9_Y10_N6; Fanout = 3; REG Node = '74160:inst3|9'
                Info: 9: + IC(0.550 ns) + CELL(0.114 ns) = 19.537 ns; Loc. = LC_X9_Y10_N2; Fanout = 4; COMB Node = '74160:inst3|49~26'
                Info: 10: + IC(3.785 ns) + CELL(0.711 ns) = 24.033 ns; Loc. = LC_X1_Y2_N2; Fanout = 3; REG Node = '74160:inst4|7'
                Info: Total cell delay = 6.376 ns ( 26.53 % )
                Info: Total interconnect delay = 17.657 ns ( 73.47 % )
            Info: - Longest clock path from clock "40MHz" to source register is 24.937 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = '40MHz'
                Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N8; Fanout = 3; REG Node = '74160:inst|9'
                Info: 3: + IC(0.564 ns) + CELL(0.292 ns) = 4.022 ns; Loc. = LC_X27_Y10_N2; Fanout = 4; COMB Node = '74160:inst|49~26'
                Info: 4: + IC(3.429 ns) + CELL(0.935 ns) = 8.386 ns; Loc. = LC_X7_Y9_N2; Fanout = 5; REG Node = '74160:inst1|6'
                Info: 5: + IC(0.583 ns) + CELL(0.292 ns) = 9.261 ns; Loc. = LC_X7_Y9_N0; Fanout = 4; COMB Node = '74160:inst1|49~26'
                Info: 6: + IC(3.966 ns) + CELL(0.935 ns) = 14.162 ns; Loc. = LC_X8_Y10_N9; Fanout = 5; REG Node = '74160:inst2|6'
                Info: 7: + IC(0.586 ns) + CELL(0.292 ns) = 15.040 ns; Loc. = LC_X8_Y10_N2; Fanout = 4; COMB Node = '74160:inst2|49~26'
                Info: 8: + IC(3.463 ns) + CELL(0.935 ns) = 19.438 ns; Loc. = LC_X9_Y10_N5; Fanout = 5; REG Node = '74160:inst3|6'
                Info: 9: + IC(0.561 ns) + CELL(0.442 ns) = 20.441 ns; Loc. = LC_X9_Y10_N2; Fanout = 4; COMB Node = '74160:inst3|49~26'
                Info: 10: + IC(3.785 ns) + CELL(0.711 ns) = 24.937 ns; Loc. = LC_X1_Y2_N9; Fanout = 3; REG Node = '74160:inst4|9'
                Info: Total cell delay = 7.238 ns ( 29.03 % )
                Info: Total interconnect delay = 17.699 ns ( 70.97 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "40MHz" to destination pin "400Hz" through register "74160:inst4|6" is 29.398 ns
    Info: + Longest clock path from clock "40MHz" to source register is 24.937 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = '40MHz'
        Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N8; Fanout = 3; REG Node = '74160:inst|9'
        Info: 3: + IC(0.564 ns) + CELL(0.292 ns) = 4.022 ns; Loc. = LC_X27_Y10_N2; Fanout = 4; COMB Node = '74160:inst|49~26'
        Info: 4: + IC(3.429 ns) + CELL(0.935 ns) = 8.386 ns; Loc. = LC_X7_Y9_N2; Fanout = 5; REG Node = '74160:inst1|6'
        Info: 5: + IC(0.583 ns) + CELL(0.292 ns) = 9.261 ns; Loc. = LC_X7_Y9_N0; Fanout = 4; COMB Node = '74160:inst1|49~26'
        Info: 6: + IC(3.966 ns) + CELL(0.935 ns) = 14.162 ns; Loc. = LC_X8_Y10_N9; Fanout = 5; REG Node = '74160:inst2|6'
        Info: 7: + IC(0.586 ns) + CELL(0.292 ns) = 15.040 ns; Loc. = LC_X8_Y10_N2; Fanout = 4; COMB Node = '74160:inst2|49~26'
        Info: 8: + IC(3.463 ns) + CELL(0.935 ns) = 19.438 ns; Loc. = LC_X9_Y10_N5; Fanout = 5; REG Node = '74160:inst3|6'
        Info: 9: + IC(0.561 ns) + CELL(0.442 ns) = 20.441 ns; Loc. = LC_X9_Y10_N2; Fanout = 4; COMB Node = '74160:inst3|49~26'
        Info: 10: + IC(3.785 ns) + CELL(0.711 ns) = 24.937 ns; Loc. = LC_X1_Y2_N3; Fanout = 5; REG Node = '74160:inst4|6'
        Info: Total cell delay = 7.238 ns ( 29.03 % )
        Info: Total interconnect delay = 17.699 ns ( 70.97 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.237 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N3; Fanout = 5; REG Node = '74160:inst4|6'
        Info: 2: + IC(0.579 ns) + CELL(0.442 ns) = 1.021 ns; Loc. = LC_X1_Y2_N6; Fanout = 1; COMB Node = '74160:inst4|49~26'
        Info: 3: + IC(1.092 ns) + CELL(2.124 ns) = 4.237 ns; Loc. = PIN_33; Fanout = 0; PIN Node = '400Hz'
        Info: Total cell delay = 2.566 ns ( 60.56 % )
        Info: Total interconnect delay = 1.671 ns ( 39.44 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Jan 03 16:25:02 2008
    Info: Elapsed time: 00:00:02