📄 fengpin.tan.rpt
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Timing Analyzer report for fengpin
Thu Jan 03 16:25:02 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: '40MHz'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 29.398 ns ; 74160:inst4|6 ; 400Hz ; 40MHz ; -- ; 0 ;
; Clock Setup: '40MHz' ; N/A ; None ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst4|9 ; 74160:inst4|7 ; 40MHz ; 40MHz ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; 40MHz ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: '40MHz' ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst4|9 ; 74160:inst4|7 ; 40MHz ; 40MHz ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst4|9 ; 74160:inst4|9 ; 40MHz ; 40MHz ; None ; None ; 1.299 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst4|8 ; 74160:inst4|9 ; 40MHz ; 40MHz ; None ; None ; 1.147 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst4|8 ; 74160:inst4|8 ; 40MHz ; 40MHz ; None ; None ; 1.141 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst4|7 ; 74160:inst4|9 ; 40MHz ; 40MHz ; None ; None ; 1.057 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst4|7 ; 74160:inst4|7 ; 40MHz ; 40MHz ; None ; None ; 1.055 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst4|7 ; 74160:inst4|8 ; 40MHz ; 40MHz ; None ; None ; 1.055 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst3|8 ; 74160:inst3|9 ; 40MHz ; 40MHz ; None ; None ; 1.273 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst4|6 ; 74160:inst4|6 ; 40MHz ; 40MHz ; None ; None ; 0.904 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst4|6 ; 74160:inst4|9 ; 40MHz ; 40MHz ; None ; None ; 0.904 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst4|6 ; 74160:inst4|7 ; 40MHz ; 40MHz ; None ; None ; 0.904 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst4|6 ; 74160:inst4|8 ; 40MHz ; 40MHz ; None ; None ; 0.904 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|7 ; 74160:inst2|8 ; 40MHz ; 40MHz ; None ; None ; 1.394 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst3|6 ; 74160:inst3|7 ; 40MHz ; 40MHz ; None ; None ; 1.167 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst3|6 ; 74160:inst3|9 ; 40MHz ; 40MHz ; None ; None ; 1.161 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst3|7 ; 74160:inst3|8 ; 40MHz ; 40MHz ; None ; None ; 1.131 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|6 ; 74160:inst2|9 ; 40MHz ; 40MHz ; None ; None ; 1.312 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|6 ; 74160:inst2|8 ; 40MHz ; 40MHz ; None ; None ; 1.311 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst3|7 ; 74160:inst3|9 ; 40MHz ; 40MHz ; None ; None ; 1.043 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst3|7 ; 74160:inst3|7 ; 40MHz ; 40MHz ; None ; None ; 1.041 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst3|8 ; 74160:inst3|8 ; 40MHz ; 40MHz ; None ; None ; 1.027 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|7 ; 74160:inst1|9 ; 40MHz ; 40MHz ; None ; None ; 1.381 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|7 ; 74160:inst1|8 ; 40MHz ; 40MHz ; None ; None ; 1.379 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|7 ; 74160:inst1|7 ; 40MHz ; 40MHz ; None ; None ; 1.378 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|7 ; 74160:inst2|9 ; 40MHz ; 40MHz ; None ; None ; 1.119 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|7 ; 74160:inst2|7 ; 40MHz ; 40MHz ; None ; None ; 1.118 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|6 ; 74160:inst1|8 ; 40MHz ; 40MHz ; None ; None ; 1.317 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst3|6 ; 74160:inst3|8 ; 40MHz ; 40MHz ; None ; None ; 0.885 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst3|6 ; 74160:inst3|6 ; 40MHz ; 40MHz ; None ; None ; 0.879 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst1|6 ; 74160:inst1|9 ; 40MHz ; 40MHz ; None ; None ; 1.310 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst3|9 ; 74160:inst3|7 ; 40MHz ; 40MHz ; None ; None ; 0.859 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst3|9 ; 74160:inst3|9 ; 40MHz ; 40MHz ; None ; None ; 0.851 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74160:inst2|6 ; 74160:inst2|7 ; 40MHz ; 40MHz ; None ; None ; 1.066 ns ;
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