init.s

做的是LCD液晶显示实验

;#line 1 "<stdin>"
; $Id: 
; 







;#line 1 "C:\Triscend\SDK_2.6\Triscend\a7hal\include\hal_conf.h"
 


 







 











 















 





 







































 



 







 





























 





 




 




 




 




 




 




 



















 















;#line 11 "<stdin>"

Mode_USR        EQU     0x10
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_FIQ        EQU     0x11

I_Bit           EQU     0x80
F_Bit           EQU     0x40

REMAP_ALIAS_ENABLE_REG	EQU	0xd1010440
MSS_SDR_CTRL_REG        EQU     0xd101000c
SYS_POWER_CTRL_REG      EQU     0xd1010110
SYS_CLOCK_CTRL_REG      EQU     0xd1010100
SYS_PLL_STATUS_REG      EQU     0xd1010104
SYS_PLL_STATUS_CLEAR_REG EQU    0xd1010108
RMAP_PAUSE_REG          EQU     0xd1010400

    IMPORT  |Image$$.text$$Limit|       ; End of ROM code (=start of ROM data)
    IMPORT  |Image$$RW$$Base|           ; Base of RAM to initialise
    IMPORT  |Image$$RW$$ZI$$Base|       ; Base and limit of area
    IMPORT  |Image$$RW$$ZI$$Limit|      ; to zero initialise

    IF :LNOT: :DEF: _NO_C_LIB
	    IMPORT  __use_no_semihosting_swi
    ENDIF
    IMPORT  a7hal_icu_IRQExit
    IMPORT  a7hal_icu_IRQEnter
    IMPORT  __IMAGE_DEST_ADDRESS
    IMPORT  __PHYSICAL_EXEC_ADDRESS
    IMPORT  __ALIAS_SETTING
    IMPORT  __STACK_TOP
    IMPORT  __STACK_SIZE

    AREA    vectors, CODE

    EXPORT  __begin
    EXPORT  _main
    EXPORT  __vectorend
    EXPORT  Hardware_Vector0
    IF :DEF: _NO_C_LIB
        EXPORT  __main
    ENDIF

    ENTRY

    IF :DEF: _NO_C_LIB
__main
    ENDIF
_main
__begin
        LDR	PC,Start_Addr
Udef
	B	Udef
SWI
	LDR	PC, SWI_Wrapper_Addr
Prefetch
	B	Prefetch
Abort		
    	LDR     PC, Abort_Wrapper_Addr
Res
        NOP
IRQ
        LDR     PC, IRQ_Wrapper_Addr
FIQ
	LDR     PC, FIQ_Wrapper_Addr

; 







Hardware_Vector0
	DCD	0
Hardware_Vector1
	DCD	0
Hardware_Vector2
	DCD	0
Hardware_Vector3
	DCD	0
Hardware_Vector4
	DCD	0
Hardware_Vector5
	DCD	0
Hardware_Vector6
	DCD	0
Hardware_Vector7
	DCD	0

SWI_Wrapper_Addr
	DCD	SWI_Wrapper
Abort_Wrapper_Addr
        DCD     Abort_Wrapper
IRQ_Wrapper_Addr
	DCD	IRQ_Wrapper
FIQ_Wrapper_Addr
	DCD	FIQ_Wrapper
Start_Addr
	DCD	Start

 ;
 ; Registers used by this function:
 ; R3 = interrupt status
 ; R4 = SDRAM_CTRL_REG
 ; R5 = CLOCK_CTRL_REG
 ;

    EXPORT  _a7hal_power_lowPower
_a7hal_power_lowPower

	STMDB	SP!,{R3-R5}		; Save the registers we need to use

        ;
        ; Save the current interrupt status
        ;
        MRS     R0,CPSR
	MOV	R3,R0

        ;
        ; Disable interrupts
        ;
        ORR     R0,R0,#I_Bit | F_Bit
        MSR     CPSR_c,R0

        ;
        ; Save the value of the SDRAM
        ; control register.
        ;
        LDR     R0,SDRAM_CTRL_REG
        LDR     R1,[R0,#0]
        MOV     R4,R1

        ;
        ; Put the SDRAM into self refresh
        ; mode.
        ;
        BIC     R1,R1,#0x07
        ORR     R1,R1,#0x00000004
        STR     R1,[R0,#0]

        ;
        ; Save the value of the clock
        ; control register.
        ;
        LDR     R0,CLOCK_CTRL_REG
        LDR     R1,[R0,#0]
	MOV	R5,R1

        ;
        ; Switch the clock to the
        ; internal ring oscillator
        ;
        BIC     R1,R1,#0x01
        STR     R1,[R0,#0]

	;
	; Now disable the PLL and
	; crystal oscillator
	;
	BIC	R1,R1,#0x10
	BIC	R1,R1,#0x20
	STR	R1,[R0,#0]

        ; Power down

        LDR     R0,POWER_DOWN_CTRL_REG
        MOV     R1,#0x2f
        STR     R1,[R0,#0]

        ORR     R1,R1,#0x10
        STR     R1,[R0,#0]

        ;
        ; The CPU will continue from this
        ; point after it wakes up
        ;
	; Check to see if we need to use the PLL
	; if not branch over the PLL init code.
	;
	MOV	R1,R5
	ANDS	R2,R1,#0x20
	BEQ	noPLL

    IF :DEF: A7V
	;
	; The A7V CSoC device family require
	; a delay for the PLL to lock.
	;
	LDR	R0,delay
pllDelay
	SUBS	R0,R0,#1
	BNE	pllDelay

    ELSE

        ;
        ; Clear the PLL status register
        ;
        LDR     R0,PLL_STATUS_CLEAR_REG
        MOV     R1,#0x03
        STR     R1,[R0,#0]

	;
	; Restore the clock control reg.
	; but do not use the PLL yet
	;
	LDR	R0,CLOCK_CTRL_REG
	MOV	R1,R5
	BIC	R1,R1,#0x01
	STR	R1,[R0,#0]

        ;
        ; Wait for the PLL Locked bit
        ;
        LDR     R0,PLL_STATUS_REG
locked
        LDR     R1,[R0,#0]
        ANDS    R1,R1,#0x02
        BEQ     locked

    ENDIF

noPLL

        ;
        ; Restore the clock control reg.
        ;
        LDR     R0,CLOCK_CTRL_REG
        MOV     R1,R5
        STR     R1,[R0,#0]

        ;
        ; Restore the SDRAM control reg.
        ;
        LDR     R0,SDRAM_CTRL_REG
        MOV     R1,R4
        STR     R1,[R0,#0]

        ;
	; Give the SDRAM time to enter normal mode
	; before we change to the ring oscillator.
	;
        LDR	R1,SDRAM_DELAY
sdram_delay_loop
	SUBS	R1,R1,#1
	BNE	sdram_delay_loop

        ;
        ; Restore the interrupt status
        ;
        MSR     CPSR_c,R3

	LDMIA 	SP!,{R3-R5}		; restore the registers

    IF :DEF: __THUMB__
        BX      LR
    ELSE
        MOV     PC,LR
    ENDIF

    IF :DEF: A7V
delay
	DCD	( ( 500 * ( 30000000 / 32768 ) ) / 4 )
    ENDIF

;
; The addresses of the A7 registers are stored here
; to prevent the linker from putting them into SDRAM
; which we put into self refresh.
;
SDRAM_DELAY
	DCD	500000
SDRAM_CTRL_REG
        DCD	MSS_SDR_CTRL_REG
POWER_DOWN_CTRL_REG
        DCD     SYS_POWER_CTRL_REG
CLOCK_CTRL_REG
        DCD     SYS_CLOCK_CTRL_REG
PAUSE_REG
        DCD     RMAP_PAUSE_REG
PLL_STATUS_REG
        DCD     SYS_PLL_STATUS_REG
PLL_STATUS_CLEAR_REG
        DCD     SYS_PLL_STATUS_CLEAR_REG

__vectorend

	AREA    |.text|, CODE, READONLY
	;
	; Abort Wrapper saves all of the registers and
	; branches to the 'C' routine to handle the
	; abort passing the address of the instruction
	; that cause the abort in R0.
	;
	IMPORT	a7hal_icu_abortMain
Abort_Wrapper
    IF :DEF: __THUMB__

	SUB	LR,LR,#5
	SUB     R0, LR, #3          	; Address of instruction that caused abort

    ELSE

	SUB	LR,LR,#4

    ENDIF

	STMDB	SP!,{R0-IP,LR}		; Store all of the registers

    IF :DEF: __THUMB__

	LDR	R12,=a7hal_icu_abortMain
	BL	thumb_call

    ELSE

	SUB     R0, LR, #4          	; Address of instruction that caused abort