swfct.c

Switch,Ic,driver,英飛凌6996m驅動程式,包括bandwidth-control以及basic-control功能

        if (value == entryIndex)
            break;
    }

    ifr.regAddr = SWI_ADDRTBL_STATREG0;
    value = SWI_ioctl(SWI_IOC_READSMI, &ifr);

#ifdef  DBG
    printf("SWIGMPTableRead: Get reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    macAddr[2] = (byte)(value & 0xff);
    macAddr[1] = (byte)((value >> 8) & 0xff);

    ifr.regAddr = SWI_ADDRTBL_STATREG1;
    value = SWI_ioctl(SWI_IOC_READSMI, &ifr);

#ifdef  DBG
    printf("reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif

    macAddr[0] = (byte)(value & 0x07f);
    *portMapVal = (value >> SWI_IGMPTBL_PORTMAP_OFFSET) & 0x3f;

    ifr.regAddr = SWI_ADDRTBL_STATREG3;
    *entryState = SWI_ioctl(SWI_IOC_READSMI, &ifr) & SWI_IGMPTBL_OCCUPY_BIT;

#ifdef  DBG
    printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    *entryState >>= SWI_IGMPTBL_OCCUPY_OFFSET;

    ifr.regAddr = SWI_ADDRTBL_STATREG5;
    value = SWI_ioctl(SWI_IOC_READSMI, &ifr);

#ifdef  DBG
    printf("reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif

    value &= SWI_LRNTBL_RESULT_BIT;
    return(value >> SWI_LRNTBL_RESULT_OFFSET);
}


int     SWIGMPTableWrite(int entryIndex, word *portMap)
{
    word value, commandCode, entryState, portMapRead, portMapVal = 0;
    byte macAddr[SWI_IGMP_MACADDR_LENGTH];
    int i, retVal;

    ifr.regAddr = SWI_ADDRTBL_STATREG5;
    value = SWI_ioctl(SWI_IOC_READSMI, &ifr);

    for (i = 0; i < 100; i++) {

        if (!(value & SWI_LRNTABL_ACCESS_BUSY)) 

            break;
        else { 

            delay(5);
            value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
        }
    }
    if (i == 100) {

        return(SWI_COMMAND_ENTRY_BUSY);
    }

   for (i = 0; i < SWI_MAX_PORT_NUMBER; i++) {

        if (portMap[i])
            portMapVal |= (1 << i);    
    }

    retVal = SWIGMPTableRead(entryIndex, &entryState, &portMapRead, macAddr);

    if (retVal)
        return(retVal);

    portMapVal |= portMapRead;

    value = ((word)macAddr[1] & 0x0ff) << 8;
    value |= ((word)macAddr[2] & 0x0ff);
    ifr.regAddr = SWI_ADDRTBL_CTRLREG0;
    ifr.regVal = (dword)value;
    SWI_ioctl(SWI_IOC_WRITESMI, &ifr);

#ifdef  DBG
    printf("SWIGMPTableWrite: reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    portMapVal <<= SWI_IGMPTBL_PORTMAP_OFFSET;
    value = ((word)macAddr[0] & 0x07f) | (portMapVal & SWI_IGMPTBL_PORTMAP_BIT);
    ifr.regAddr = SWI_ADDRTBL_CTRLREG1;
    ifr.regVal = (dword)value;
    SWI_ioctl(SWI_IOC_WRITESMI, &ifr);

#ifdef  DBG
    printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    ifr.regAddr = SWI_ADDRTBL_CTRLREG2;
    ifr.regVal = 0;
    SWI_ioctl(SWI_IOC_WRITESMI, &ifr);

#ifdef  DBG
    printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    entryState <<= SWI_IGMPTBL_OCCUPY_OFFSET;
    ifr.regAddr = SWI_ADDRTBL_CTRLREG3;
    ifr.regVal = (dword)entryState;
    SWI_ioctl(SWI_IOC_WRITESMI, &ifr);

#ifdef  DBG
    printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    ifr.regAddr = SWI_ADDRTBL_CTRLREG4;
    ifr.regVal = (dword)entryIndex;
    SWI_ioctl(SWI_IOC_WRITESMI, &ifr);

#ifdef  DBG
    printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    commandCode = SWI_COMMAND_WRITE_IGMPTBL << SWI_LRNTBL_COMMAND_OFFSET;
    ifr.regAddr = SWI_ADDRTBL_CTRLREG5;
    ifr.regVal = (dword)commandCode;
    SWI_ioctl(SWI_IOC_WRITESMI, &ifr);

#ifdef  DBG
    printf("reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif

    ifr.regAddr = SWI_ADDRTBL_STATREG5;
    value = SWI_ioctl(SWI_IOC_READSMI, &ifr);

    for (i = 0; i < 100; i++) {

        if (!(value & SWI_LRNTABL_ACCESS_BUSY)) 

            break;
        else { 

            delay(5);
            value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
        }
    }
    if (i == 100) {

        return(SWI_COMMAND_ENTRY_BUSY);
    }

    value &= SWI_LRNTBL_RESULT_BIT;
    return(value >> SWI_LRNTBL_RESULT_OFFSET);
}


int SWResetPortCounter(int port_no) // add - 06/16/05,bolo
{
    dword   value;
    int i;

    ifr.regAddr = SWI_COUNTER_CTRLLOW;
    SWI_ioctl(SWI_IOC_READSMI, &ifr);
    value = ifr.regVal & 0xff;

    for (i = 0; i < 100; i++) {

        if (!(value & SWI_COUNTER_BUSY_BIT)) 
    
            break;
        else { 

            delay(5);
            value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
            value = ifr.regVal & 0xff;
        }
    }
    if (i == 100) {

        return(SWI_ACCESS_COUNTER_BUSY);
    }

    value = 1 << port_no;
    value |= SWI_RENEW_PORT_COUNTER;
    ifr.regVal = (dword)value;
    SWI_ioctl(SWI_IOC_WRITESMI, &ifr);
    SWI_ioctl(SWI_IOC_READSMI, &ifr);
    value = ifr.regVal & 0xff;

    for (i = 0; i < 100; i++) {

        if (!(value & SWI_COUNTER_BUSY_BIT)) 

            break;
        else { 

            delay(5);
            value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
            value = ifr.regVal & 0xff;
        }
    }
    if (i == 100) {

        return(SWI_ACCESS_COUNTER_BUSY);
    }
    return(SWI_ACCESS_COUNTER_FREE);
}


dword   SWPortCounter(int port_no, int regIndex)
{
    dword   value;
    word    portShift[] = {0, 4, 8, 12, 14, 16};
    
    ifr.regAddr = SWI_PORT0_RXPKTCL + portShift[port_no] + regIndex * SWI_COUNTER_OFFSET;
    SWI_ioctl(SWI_IOC_READSMI, &ifr);
    value = ifr.regVal & 0xffff;

#ifdef  DBG
    printf("\nSWPortCounter: regL[%#x]=%#lx, value=%#lx, ", ifr.regAddr, ifr.regVal, value);
#endif

    ifr.regAddr += SWI_COUNTER_HIGH_REG;
    value |= SWI_ioctl(SWI_IOC_READSMI, &ifr)* 0x10000;

#ifdef  DBG
    printf("regH[%#x]=%#lx, value=%#lx\n", ifr.regAddr, ifr.regVal, value);
#endif

    return(value);
}


word ReadPhyReg(int port_no, int regAddr)
{
    ifr.regAddr = SWI_PHYREG_START_ADDR + port_no * SWI_PHYREG_OFFSET + regAddr;
    SWI_ioctl(SWI_IOC_READSMI, &ifr);

#ifdef  DBG
    printf("ReadPhyReg: reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif

    return(ifr.regVal);
}
    

void WritePhyReg(int port_no, int regAddr, word regValue)
{
    ifr.regAddr = SWI_PHYREG_START_ADDR + port_no * SWI_PHYREG_OFFSET + regAddr;
    ifr.regVal = (dword)regValue;
    SWI_ioctl(SWI_IOC_WRITESMI, &ifr);

#ifdef  DBG
    printf("WritePhyReg: reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif

} 


// Read a word from register, add - 06/27/05,bolo
word    ReadEEPROM(word address)
{
    ifr.regAddr = address;
    ifr.regVal = 0;
    SWI_ioctl(SWI_IOC_READEEPROM, &ifr);

#ifdef  DBG
    printf("ReadEEPROM: eep[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif

    return((word)ifr.regVal);
}

// Write a word into EEPROM register
void    WriteEEPROM(word address, word value)
{
    ifr.regAddr = address;
    ifr.regVal = (dword)value;
    SWI_ioctl(SWI_IOC_WRITEEEPROM, &ifr);

#ifdef  DBG
    printf("WriteEEPROM: eep[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif

}

// Read data through SMI interface
dword   ReadSMI(word address)
{
    ifr.regAddr = address;
    ifr.regVal = 0;
    SWI_ioctl(SWI_IOC_READSMI, &ifr);

#ifdef  DBG
    printf("ReadSMI: reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif

    return(ifr.regVal);
}


// Write data through SMI interface
void    WriteSMI(word address, dword value)
{
    ifr.regAddr = address;
    ifr.regVal = value;
    SWI_ioctl(SWI_IOC_WRITESMI, &ifr);

#ifdef  DBG
    printf("WriteSMI: reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif

}


// Reset switch, add - 06/24/05,bolo
void SWI_Reset(void)
{
    SWI_ioctl(SWI_IOC_RESET, NULL);
}


word    SWI_ioctl(word cmd, PREGRW ifr)
{
    word result = 0;
	int  fd; // add - 06/24/05

	fd = open("/dev/adm6996i", O_RDWR, 0);

    if (fd == -1) {

        printf("The ADM6996I/M driver is not installed !\n");    
        return SWI_ACCESS_ERROR;
    }

	switch (cmd) {

#ifdef  EEPROM
		case SWI_IOC_READEEPROM:

            if (ioctl(fd, ADM_SWI_IOC_READEEPROM, ifr))
            {
                printf("IOCTL: read error at EEPROM register !\n");
                return SWI_ACCESS_ERROR;
            }
            result = ifr->regVal;
			break;

		case SWI_IOC_WRITEEEPROM:
	  
            if (ioctl(fd, ADM_SWI_IOC_WRITEEEPROM, ifr))
            {
                printf("IOCTL: write error at EEPROM register !\n");
                return SWI_ACCESS_ERROR;
            }
			break;
#endif

		case SWI_IOC_READSMI:

            if (ioctl(fd, ADM_SWI_IOC_READSMI, ifr))
            {
                printf("IOCTL: SMI read error in the internal register !\n");
                return SWI_ACCESS_ERROR;
            }
            result = ifr->regVal;
			break;

		case SWI_IOC_WRITESMI:

            if (ioctl(fd, ADM_SWI_IOC_WRITESMI, ifr))
            {
                printf("IOCTL: SMI write error in the internal register !\n");
                return SWI_ACCESS_ERROR;
            }
			break;

		case SWI_IOC_INIT:

            ioctl(fd, ADM_SWI_IOC_INIT, NULL);
            break;

		case SWI_IOC_RESET:

            ioctl(fd, ADM_SWI_IOC_RESET, NULL);
            break;

		default:
			return SWI_ACCESS_ERROR;
	}
    return result;
}