📄 swfct.c
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value = (macAddr[j-1] << 8);
value |= macAddr[j];
if (i != 2)
j -= 2;
ifr.regAddr = SWI_ADDRTBL_CTRLREG0 + i;
ifr.regVal = (dword)value;
SWI_ioctl(SWI_IOC_WRITESMI, &ifr);
#ifdef DBG
printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
}
#ifdef DBG
printf("\n");
#endif
ifr.regAddr = SWI_ADDRTBL_CTRLREG3;
ifr.regVal = (dword)(*fidVal | (portMapVal << SWI_LRNTBL_PORTMAP_OFFSET));
SWI_ioctl(SWI_IOC_WRITESMI, &ifr);
#ifdef DBG
printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
ifr.regAddr = SWI_ADDRTBL_CTRLREG4;
ifr.regVal = 0;
SWI_ioctl(SWI_IOC_WRITESMI, &ifr);
#ifdef DBG
printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
ifr.regAddr = SWI_ADDRTBL_CTRLREG5;
ifr.regVal = (dword)(SWI_COMMAND_INITIAL_MAC << SWI_LRNTBL_COMMAND_OFFSET);
SWI_ioctl(SWI_IOC_WRITESMI, &ifr);
#ifdef DBG
printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
ifr.regAddr = SWI_ADDRTBL_CTRLREG5;
ifr.regVal = (dword)accessCode;
SWI_ioctl(SWI_IOC_WRITESMI, &ifr);
#ifdef DBG
printf("reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif
ifr.regAddr = SWI_ADDRTBL_STATREG5;
value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
for (i = 0; i < 100; i++) {
if (!(value & SWI_LRNTABL_ACCESS_BUSY))
break;
else {
delay(5);
value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
}
}
if (i == 100) {
return(SWI_COMMAND_ENTRY_BUSY);
}
#ifdef DBG
printf("\nSWLearnTableRead: Get >> ");
#endif
for (i = 0, j = 5; i < 3; i++) {
ifr.regAddr = SWI_ADDRTBL_STATREG0 + i;
value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
#ifdef DBG
printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
macAddr[j-1] = (byte)((value >> 8) & 0xff);
macAddr[j] = (byte)(value & 0xff);
if (i != 2)
j -= 2;
}
#ifdef DBG
printf("\n");
#endif
ifr.regAddr = SWI_ADDRTBL_STATREG3;
*fidVal= SWI_ioctl(SWI_IOC_READSMI, &ifr) & SWI_LRNTBL_FID_BIT;
#ifdef DBG
printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
portMap[6]= SWI_ioctl(SWI_IOC_READSMI, &ifr) & SWI_LRNTBL_PORTMAP_BIT;
portMap[6] >>= SWI_LRNTBL_PORTMAP_OFFSET;
ifr.regAddr = SWI_ADDRTBL_STATREG4;
*infoCtrlAge = SWI_ioctl(SWI_IOC_READSMI, &ifr) & SWI_LRNTBL_INFOCTRL_BIT;
#ifdef DBG
printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
ifr.regAddr = SWI_ADDRTBL_STATREG5;
value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
#ifdef DBG
printf("reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif
*entryStatus = value;
value &= SWI_LRNTBL_RESULT_BIT;
return(value >> SWI_LRNTBL_RESULT_OFFSET);
}
int SWLearnTableWrite(int accessControl, int addrType, word infoCtrlAge, word *portMap, int fidVal, byte *macAddr)
{
word value, commandCode, portMapVal = 0;
int i, j;
for (i = 0; i < SWI_MAX_PORT_NUMBER; i++) {
if (portMap[i])
portMapVal |= (1 << i);
}
ifr.regAddr = SWI_ADDRTBL_STATREG5;
value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
for (i = 0; i < 100; i++) {
if (!(value & SWI_LRNTABL_ACCESS_BUSY))
break;
else {
delay(5);
value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
}
}
if (i == 100) {
return(SWI_COMMAND_ENTRY_BUSY);
}
#ifdef DBG
printf("SWLearnTableWrite: ");
#endif
for (i = 0, j = 5; i < 3; i++) {
value = (macAddr[j-1] << 8);
value |= macAddr[j];
if (i != 2)
j -= 2;
ifr.regAddr = SWI_ADDRTBL_CTRLREG0 + i;
ifr.regVal = (dword)value;
SWI_ioctl(SWI_IOC_WRITESMI, &ifr);
#ifdef DBG
printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
}
#ifdef DBG
printf("\n");
#endif
ifr.regAddr = SWI_ADDRTBL_CTRLREG3;
ifr.regVal = (dword)(fidVal | (portMapVal << SWI_LRNTBL_PORTMAP_OFFSET));
SWI_ioctl(SWI_IOC_WRITESMI, &ifr);
#ifdef DBG
printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
ifr.regAddr = SWI_ADDRTBL_CTRLREG4;
ifr.regVal = (dword)(infoCtrlAge | (addrType << SWI_LRNTBL_INFOTYPE_OFFSET));
SWI_ioctl(SWI_IOC_WRITESMI, &ifr);
#ifdef DBG
printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
commandCode = SWI_COMMAND_WRITE_MAC;
switch (accessControl) {
case 1:
/*
value = SWI_ACCESS_CREATE_NEWMAC;
*/
ifr.regVal = SWI_ACCESS_CREATE_NEWMAC;
break;
case 2:
/*
value = SWI_ACCESS_OVERWRITE_MAC;
*/
ifr.regVal = SWI_ACCESS_OVERWRITE_MAC;
break;
case 3:
/*
value = SWI_ACCESS_ERASE_MAC;
*/
ifr.regVal = SWI_ACCESS_ERASE_MAC;
commandCode = SWI_COMMAND_ERASE_MAC;
break;
default:
/*
value = SWI_ACCESS_CREATE_NEWMAC;
*/
ifr.regVal = SWI_ACCESS_CREATE_NEWMAC;
break;
}
ifr.regVal |= (commandCode << SWI_LRNTBL_COMMAND_OFFSET);
ifr.regAddr = SWI_ADDRTBL_CTRLREG5;
SWI_ioctl(SWI_IOC_WRITESMI, &ifr);
#ifdef DBG
printf("reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif
ifr.regAddr = SWI_ADDRTBL_STATREG5;
value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
for (i = 0; i < 100; i++) {
if (!(value & SWI_LRNTABL_ACCESS_BUSY))
break;
else {
delay(5);
value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
}
}
if (i == 100) {
return(SWI_COMMAND_ENTRY_BUSY);
}
value &= SWI_LRNTBL_RESULT_BIT;
return(value >> SWI_LRNTBL_RESULT_OFFSET);
}
void SWIGMPConfig(int igmpEnable, int ignoreCPUPort, int queryInterval, int robustVariable, word *routerPortMap)
{
int i;
word routerMapVal = 0;
ifr.regAddr = SWI_HWIGMP_CTRLREG;
ifr.regVal = queryInterval << SWI_IGMP_QRYINTERVAL_OFFSET;
ifr.regVal |= (robustVariable << SWI_IGMP_ROBUSTVAR_OFFSET);
for (i = 0; i < SWI_MAX_PORT_NUMBER; i++) {
if (routerPortMap[i])
routerMapVal |= (1 << i);
}
ifr.regVal |= routerMapVal;
SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI
#ifdef DBG
printf("SWIGMPConfig: reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
if (routerMapVal)
ifr.regVal = SWI_IGMP_ROUTER_ENABLE_BIT;
else
ifr.regVal = 0;
if (igmpEnable)
ifr.regVal |= SWI_IGMP_SNOOP_ENABLE_BIT;
if (ignoreCPUPort)
ifr.regVal |= SWI_IGMP_IGNORE_CPUPORT_BIT;
ifr.regAddr = SWI_MCSTSNOOP_CTRLREG;
SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI
#ifdef DBG
printf("reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif
}
void SWIGMPOptConfig(int igmpOptItem, word igmpOptVal)
{
word value;
// 0: Trap IGMP_IP packet, 1: IGMP packet as Cross_VLAN packet, 2: IGMP packet priority enable
// 3: IGMP packet priority, 4: IGMP packet transmission TAG handle, 5: IGMP packet action,
// 6: Additional IGMP control, 7: Source Violation over IGMP, 8: Source Violation over Default
struct REGBIT_OFFSET_DEF igmpOptReg[] = {{SWI_MCSTSNOOP_CTRLREG, SWI_TRAP_IGMP_PACKET_BIT, SWI_TRAP_IGMP_PACKET_OFFSET},
{SWI_MCSTSNOOP_CTRLREG, SWI_IGMP_CROSS_VLAN_BIT, SWI_IGMP_CROSS_VLAN_OFFSET},
{SWI_MCSTSNOOP_CTRLREG, SWI_IGMP_PKT_PRIEN_BIT, SWI_IGMP_PKT_PRIEN_OFFSET},
{SWI_MCSTSNOOP_CTRLREG, SWI_IGMP_PACKET_PRI_BIT, SWI_IGMP_PACKET_PRI_OFFSET},
{SWI_MCSTSNOOP_CTRLREG, SWI_IGMP_PKT_TXTAG_BIT, SWI_IGMP_PKT_TXTAG_OFFSET},
{SWI_MCSTSNOOP_CTRLREG, SWI_IGMP_CTRL_ACTION_BIT, SWI_IGMP_CTRL_ACTION_OFFSET},
{SWI_SYSTEM_CTRLREG1, SWI_IGMP_EXTRA_CTRL_BIT, SWI_IGMP_EXTRA_CTRL_OFFSET},
{SWI_SYSTEM_CTRLREG1, SWI_SRCVIO_OVER_IGMP_BIT, SWI_SRCVIO_OVER_IGMP_OFFSET},
{SWI_SYSTEM_CTRLREG1, SWI_SRCVIO_OVER_DFLT_BIT, SWI_SRCVIO_OVER_DFLT_OFFSET}};
ifr.regAddr = igmpOptReg[igmpOptItem].regAddr;
value = SWI_ioctl(RegReadMode, &ifr) & (~ igmpOptReg[igmpOptItem].bitVal); // SWI_IOC_READEEPROM or SWI_IOC_READSMI
ifr.regVal = (dword)(value | (igmpOptVal << igmpOptReg[igmpOptItem].offset));
SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI
#ifdef DBG
printf("SWIGMPOptConfig: reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif
}
int SWIGMPTableRead(int entryIndex, word *entryState, word *portMapVal, byte *macAddr)
{
word value, commandCode;
int i, j;
ifr.regAddr = SWI_ADDRTBL_STATREG5;
value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
for (i = 0; i < 100; i++) {
if (!(value & SWI_LRNTABL_ACCESS_BUSY))
break;
else {
delay(5);
value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
}
}
if (i == 100) {
return(SWI_COMMAND_ENTRY_BUSY);
}
#ifdef DBG
printf("SWIGMPTableRead: Set ");
#endif
commandCode = SWI_COMMAND_READ_IGMPTBL << SWI_LRNTBL_COMMAND_OFFSET;
for (j = 0; j < SWI_IGMPTBL_ACCESS_MAXNUM; j++) {
ifr.regAddr = SWI_ADDRTBL_CTRLREG4;
ifr.regVal = (dword)entryIndex;
SWI_ioctl(SWI_IOC_WRITESMI, &ifr);
#ifdef DBG
if (j==0)
printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
ifr.regAddr = SWI_ADDRTBL_CTRLREG5;
ifr.regVal = (dword)commandCode;
SWI_ioctl(SWI_IOC_WRITESMI, &ifr);
#ifdef DBG
if (j==0)
printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
ifr.regAddr = SWI_ADDRTBL_STATREG5;
value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
for (i = 0; i < 100; i++) {
if (!(value & SWI_LRNTABL_ACCESS_BUSY))
break;
else {
delay(5);
value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
}
}
if (i == 100) {
return(SWI_COMMAND_ENTRY_BUSY);
}
ifr.regAddr = SWI_ADDRTBL_STATREG4;
value = SWI_ioctl(SWI_IOC_READSMI, &ifr) & SWI_IGMPTBL_ENTRY_BIT;
#ifdef DBG
printf("reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif
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