swfct.c

Switch,Ic,driver,英飛凌6996m驅動程式,包括bandwidth-control以及basic-control功能

#endif

    ifr.regAddr = SWI_VLANPRI_ENABLEMAP;
    value = SWI_ioctl(RegReadMode, &ifr) & (~ SWI_VLAN_PRIEN_BIT); // SWI_IOC_READEEPROM or SWI_IOC_READSMI

    for (i = 0; i < SWI_MAX_PORT_NUMBER; i++) {

        if (vlanPriEn[i])
            vlanPriEnMap |= (1 << i);    
    }   

    value |= (vlanPriEnMap << SWI_VLAN_PRIEN_OFFSET);
    ifr.regVal = (dword)value;
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    value = SWI_PRIQ_OPTION_VALUE;
    value <<= vlanPriOffset[priQID];
    vlanPriQOpt = vlanQOpt << vlanPriOffset[priQID];

    ifr.regAddr = SWI_VLANPRI_MAPREG;
    value = SWI_ioctl(RegReadMode, &ifr) & (~ value); // SWI_IOC_READEEPROM or SWI_IOC_READSMI
    ifr.regVal = (dword)(value | vlanPriQOpt);
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif
}


void SWTOSPriConfig(int *tosPriEn, int tospriQID, int tosQOpt)
{
    int i;
    word value, tosPriQOpt, tosPriEnMap;
    word tosPriOffset[] = {SWI_PRIQ0_MAP_OFFSET, SWI_PRIQ1_MAP_OFFSET, SWI_PRIQ2_MAP_OFFSET,
                           SWI_PRIQ3_MAP_OFFSET, SWI_PRIQ4_MAP_OFFSET, SWI_PRIQ5_MAP_OFFSET,
                           SWI_PRIQ6_MAP_OFFSET, SWI_PRIQ7_MAP_OFFSET};

    ifr.regAddr = SWI_SERVPRI_ENABLEMAP;
    value = SWI_ioctl(RegReadMode, &ifr) & (~ SWI_SERVICE_PRIEN_BIT); // SWI_IOC_READEEPROM or SWI_IOC_READSMI

    for (i = 0; i < SWI_MAX_PORT_NUMBER; i++) {

        if (tosPriEn[i])
            tosPriEnMap |= (1 << i);    
    }   

    value |= (tosPriEnMap << SWI_SERVICE_PRIEN_OFFSET);
    ifr.regVal = (dword)value;
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("SWTOSPriConfig: reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    ifr.regAddr = SWI_SYSTEM_CTRLREG0;
    value = SWI_ioctl(RegReadMode, &ifr) | SWI_TOS_USING_3BITS; // use 3-bits TOS priority, SWI_IOC_READEEPROM or SWI_IOC_READSMI
    ifr.regVal = (dword)value;
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    value = SWI_PRIQ_OPTION_VALUE;
    value <<= tosPriOffset[tospriQID];
    tosPriQOpt = tosQOpt << tosPriOffset[tospriQID];

    ifr.regAddr = SWI_TOSPRI_MAPREG;
    value = SWI_ioctl(RegReadMode, &ifr) & (~ value); // SWI_IOC_READEEPROM or SWI_IOC_READSMI
    ifr.regVal = (dword)(value | tosPriQOpt);
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif
}


void SWSrvPriConfig(int *tsrvPriEn, int tsrvpriQID, int tsrvQOpt)
{
    int i;
    word value, tsrvPriQOpt, psrvQID, regAddr, tsrvPriEnMap;
    word tsrvPriOffset[] = {SWI_PRIQ0_MAP_OFFSET, SWI_PRIQ1_MAP_OFFSET, SWI_PRIQ2_MAP_OFFSET,
                            SWI_PRIQ3_MAP_OFFSET, SWI_PRIQ4_MAP_OFFSET, SWI_PRIQ5_MAP_OFFSET,
                            SWI_PRIQ6_MAP_OFFSET, SWI_PRIQ7_MAP_OFFSET};

    ifr.regAddr = SWI_SERVPRI_ENABLEMAP;
    value = SWI_ioctl(RegReadMode, &ifr) & (~ SWI_SERVICE_PRIEN_BIT); // SWI_IOC_READEEPROM or SWI_IOC_READSMI

    for (i = 0; i < SWI_MAX_PORT_NUMBER; i++) {

        if (tsrvPriEn[i])
            tsrvPriEnMap |= (1 << i);    
    }   

    value |= (tsrvPriEnMap << SWI_SERVICE_PRIEN_OFFSET);
    ifr.regVal = (dword)value;
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("SWSrvPriConfig: reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    ifr.regAddr = SWI_SYSTEM_CTRLREG0;
    value = SWI_ioctl(RegReadMode, &ifr) & (~ SWI_TOS_USING_3BITS); // use 6-bits TOS priority, SWI_IOC_READEEPROM or SWI_IOC_READSMI
    ifr.regVal = (dword)value;
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    psrvQID = tsrvpriQID % 8;
    value = SWI_PRIQ_OPTION_VALUE;
    value <<= tsrvPriOffset[psrvQID];
    tsrvPriQOpt = tsrvQOpt << tsrvPriOffset[psrvQID];
    regAddr = SWI_SERVICE_PRI_MAPREG0 + (tsrvpriQID / 8);

    ifr.regAddr = regAddr;
    value = SWI_ioctl(RegReadMode, &ifr) & (~ value); // SWI_IOC_READEEPROM or SWI_IOC_READSMI
    ifr.regVal = (dword)(value | tsrvPriQOpt);
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif
}


void SWBrdStormConfig(int stormEnable, int dropEnable, int thres100Mbp, int thres10Mbp, int mulpktStorm)
{
    word value;

    ifr.regAddr = SWI_SYSTEM_CTRLREG3;
    value = SWI_ioctl(RegReadMode, &ifr) | SWI_NEW_STORM_ENABLE; // SWI_IOC_READEEPROM or SWI_IOC_READSMI
    ifr.regVal = (dword)value;
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("SWBrdStormConfig: reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    ifr.regAddr = SWI_NEWSTORM_CTRLREG1;
    value = SWI_ioctl(RegReadMode, &ifr) & (~ SWI_STORMDROP_THRES_BIT); // SWI_IOC_READEEPROM or SWI_IOC_READSMI
    ifr.regVal = (dword)(value | thres10Mbp);
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    ifr.regAddr = SWI_NEWSTORM_CTRLREG0;
    value = SWI_ioctl(RegReadMode, &ifr) & (~ (SWI_STORMDROP_THRES_BIT | SWI_STORM_DROP_ENABLE_BIT)); // SWI_IOC_READEEPROM or SWI_IOC_READSMI
    value |= (stormEnable << SWI_STORM_ENABLE_OFFSET);
    value |= (dropEnable << SWI_DROP_ENABLE_OFFSET);
    ifr.regVal = (dword)(value | thres100Mbp);
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    if (mulpktStorm == 2)
        return;

    ifr.regAddr = SWI_SYSTEM_CTRLREG2;
    value = SWI_ioctl(RegReadMode, &ifr) & (~ SWI_MULPKT_STORM_BIT); // SWI_IOC_READEEPROM or SWI_IOC_READSMI
    value |= (mulpktStorm << SWI_MULPKT_STORM_OFFSET);
    ifr.regVal = (dword)value;
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif
}

void SWTxBandConfig(int port_no, int txBWCEnable, int txBWThresh)
{
    int i;
    word value, regVal[3];
    word txBWCEnOffset[] = {SWI_TX0BWC_ENABLE_OFFSET, SWI_TX1BWC_ENABLE_OFFSET, SWI_TX2BWC_ENABLE_OFFSET,
                            SWI_TX3BWC_ENABLE_OFFSET, SWI_TX4BWC_ENABLE_OFFSET, SWI_TX5BWC_ENABLE_OFFSET};
    word txBWTOffset[] =   {SWI_BWT_TYPEL0_OFFSET0, SWI_BWT_TYPEL1_OFFSET0, SWI_BWT_TYPEH0_OFFSET0};
    word txBWTMask[] =     {SWI_BWT_TYPEL0_4BIT, SWI_BWT_TYPEL1_4BIT, SWI_BWT_TYPEH3_3BIT};

    struct REGBIT_OFFSET_DEF txBWTReg[3][6] = {{{SWI_BASIC_BANDWIDTH1,  SWI_BWT_TYPEH0_4BIT, SWI_BWT_TYPEH0_OFFSET0},
                                                {SWI_BASIC_BANDWIDTH1,  SWI_BWT_TYPEH1_4BIT, SWI_BWT_TYPEH1_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH0, SWI_BWT_TYPEL0_4BIT, SWI_BWT_TYPEL0_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH0, SWI_BWT_TYPEL1_4BIT, SWI_BWT_TYPEL1_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH0, SWI_BWT_TYPEH0_4BIT, SWI_BWT_TYPEH0_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH0, SWI_BWT_TYPEH1_4BIT, SWI_BWT_TYPEH1_OFFSET0}},

                                               {{SWI_EXTEND_BANDWIDTH2, SWI_BWT_TYPEH0_4BIT, SWI_BWT_TYPEH0_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH2, SWI_BWT_TYPEH1_4BIT, SWI_BWT_TYPEH1_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH3, SWI_BWT_TYPEL0_4BIT, SWI_BWT_TYPEL0_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH3, SWI_BWT_TYPEL1_4BIT, SWI_BWT_TYPEL1_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH3, SWI_BWT_TYPEH0_4BIT, SWI_BWT_TYPEH0_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH3, SWI_BWT_TYPEH1_4BIT, SWI_BWT_TYPEH1_OFFSET0}},

                                               {{SWI_EXTEND_BANDWIDTH5, SWI_BWT_TYPEL1_3BIT, SWI_BWT_TYPEL1_OFFSET1},
                                                {SWI_EXTEND_BANDWIDTH5, SWI_BWT_TYPEH0_3BIT, SWI_BWT_TYPEH0_OFFSET1},
                                                {SWI_EXTEND_BANDWIDTH5, SWI_BWT_TYPEH1_3BIT, SWI_BWT_TYPEH1_OFFSET1},
                                                {SWI_EXTEND_BANDWIDTH5, SWI_BWT_TYPEH2_3BIT, SWI_BWT_TYPEH2_OFFSET1},
                                                {SWI_EXTEND_BANDWIDTH6, SWI_BWT_TYPEL0_3BIT, SWI_BWT_TYPEL0_OFFSET1},
                                                {SWI_EXTEND_BANDWIDTH6, SWI_BWT_TYPEL1_3BIT, SWI_BWT_TYPEL1_OFFSET1}}};

    ifr.regAddr = SWI_BANDWIDTH_ENABLE;
    value = SWI_ioctl(RegReadMode, &ifr) | SWI_NEW_BWCTRL_BIT; // SWI_IOC_READEEPROM or SWI_IOC_READSMI
    value &= ~(1 << txBWCEnOffset[port_no]);
    value |= (txBWCEnable << txBWCEnOffset[port_no]);
    ifr.regVal = (dword)value;

    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("SWTxBandConfig: reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    for (i = 0; i < 3; i++) {

        ifr.regAddr = txBWTReg[i][port_no].regAddr;
        regVal[i] = SWI_ioctl(RegReadMode, &ifr) & (~ txBWTReg[i][port_no].bitVal); // SWI_IOC_READEEPROM or SWI_IOC_READSMI

        value = (txBWThresh & txBWTMask[i]) >> txBWTOffset[i];
        regVal[i] |= (value << txBWTReg[i][port_no].offset);
        ifr.regVal = (dword)regVal[i];
        SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
    }
#ifdef  DBG
    printf("\n");
#endif
}


void SWRxBandConfig(int port_no, int rxBWCEnable, int rxBWThresh)
{
    int i;
    word value, regVal[3];
    word rxBWCEnOffset[] = {SWI_RX0BWC_ENABLE_OFFSET, SWI_RX1BWC_ENABLE_OFFSET, SWI_RX2BWC_ENABLE_OFFSET,
                                  SWI_RX3BWC_ENABLE_OFFSET, SWI_RX4BWC_ENABLE_OFFSET, SWI_RX5BWC_ENABLE_OFFSET};
    word rxBWTOffset[] =   {SWI_BWT_TYPEL0_OFFSET0, SWI_BWT_TYPEL1_OFFSET0, SWI_BWT_TYPEH0_OFFSET0};
    word rxBWTMask[] =     {SWI_BWT_TYPEL0_4BIT, SWI_BWT_TYPEL1_4BIT, SWI_BWT_TYPEH3_3BIT};

    struct REGBIT_OFFSET_DEF rxBWTReg[3][6] = {{{SWI_BASIC_BANDWIDTH0,  SWI_BWT_TYPEL0_4BIT, SWI_BWT_TYPEL0_OFFSET0},
                                                {SWI_BASIC_BANDWIDTH0,  SWI_BWT_TYPEL1_4BIT, SWI_BWT_TYPEL1_OFFSET0},
                                                {SWI_BASIC_BANDWIDTH0,  SWI_BWT_TYPEH0_4BIT, SWI_BWT_TYPEH0_OFFSET0},
                                                {SWI_BASIC_BANDWIDTH0,  SWI_BWT_TYPEH1_4BIT, SWI_BWT_TYPEH1_OFFSET0},
                                                {SWI_BASIC_BANDWIDTH1,  SWI_BWT_TYPEL0_4BIT, SWI_BWT_TYPEL0_OFFSET0},
                                                {SWI_BASIC_BANDWIDTH1,  SWI_BWT_TYPEL1_4BIT, SWI_BWT_TYPEL1_OFFSET0}},

                                               {{SWI_EXTEND_BANDWIDTH1, SWI_BWT_TYPEL0_4BIT, SWI_BWT_TYPEL0_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH1, SWI_BWT_TYPEL1_4BIT, SWI_BWT_TYPEL1_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH1, SWI_BWT_TYPEH0_4BIT, SWI_BWT_TYPEH0_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH1, SWI_BWT_TYPEH1_4BIT, SWI_BWT_TYPEH1_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH2, SWI_BWT_TYPEL0_4BIT, SWI_BWT_TYPEL0_OFFSET0},
                                                {SWI_EXTEND_BANDWIDTH2, SWI_BWT_TYPEL1_4BIT, SWI_BWT_TYPEL1_OFFSET0}},

                                               {{SWI_EXTEND_BANDWIDTH4, SWI_BWT_TYPEL0_3BIT, SWI_BWT_TYPEL0_OFFSET1},
                                                {SWI_EXTEND_BANDWIDTH4, SWI_BWT_TYPEL1_3BIT, SWI_BWT_TYPEL1_OFFSET1},
                                                {SWI_EXTEND_BANDWIDTH4, SWI_BWT_TYPEH0_3BIT, SWI_BWT_TYPEH0_OFFSET1},
                                                {SWI_EXTEND_BANDWIDTH4, SWI_BWT_TYPEH1_3BIT, SWI_BWT_TYPEH1_OFFSET1},
                                                {SWI_EXTEND_BANDWIDTH4, SWI_BWT_TYPEH2_3BIT, SWI_BWT_TYPEH2_OFFSET1},
                                                {SWI_EXTEND_BANDWIDTH5, SWI_BWT_TYPEL0_3BIT, SWI_BWT_TYPEL0_OFFSET1}}};

    ifr.regAddr = SWI_BANDWIDTH_ENABLE;
    value = SWI_ioctl(RegReadMode, &ifr) | SWI_NEW_BWCTRL_BIT; // SWI_IOC_READEEPROM or SWI_IOC_READSMI
    value &= ~(1 << rxBWCEnOffset[port_no]);
    value |= (rxBWCEnable << rxBWCEnOffset[port_no]);
    ifr.regVal = (dword)value;

    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("SWRxBandConfig: reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif

    for (i = 0; i < 3; i++) {

        ifr.regAddr = rxBWTReg[i][port_no].regAddr;
        regVal[i] = SWI_ioctl(RegReadMode, &ifr) & (~ rxBWTReg[i][port_no].bitVal); // SWI_IOC_READEEPROM or SWI_IOC_READSMI
        value = (rxBWThresh & rxBWTMask[i]) >> rxBWTOffset[i];
        regVal[i] |= (value << rxBWTReg[i][port_no].offset);
        ifr.regVal = (dword)regVal[i];
        SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("reg[%#x]=%#lx, ", ifr.regAddr, ifr.regVal);
#endif
    }
#ifdef  DBG
    printf("\n");
#endif
}


void    SWPortSecurityConfig(int port_no, int portSecOpt, int closePort)
{
    word value, secOptVal;
    int  vlanReg[] = {SWI_FWDGROUP0_PORTMAP, SWI_FWDGROUP1_PORTMAP, SWI_FWDGROUP2_PORTMAP,
                      SWI_FWDGROUP3_PORTMAP, SWI_FWDGROUP4_PORTMAP, SWI_FWDGROUP5_PORTMAP};
 
    secOptVal = portSecOpt << SWI_PORT_SECURE_OPT_OFFSET;

    if (closePort == 1)
        secOptVal |= (closePort << SWI_CLOSE_PORT_OFFSET);
    
    ifr.regAddr = vlanReg[port_no];
    value = SWI_ioctl(RegReadMode, &ifr) & (~ SWI_ALL_SECURE_BIT); // SWI_IOC_READEEPROM or SWI_IOC_READSMI
    ifr.regVal = (dword)(value | secOptVal);
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("SWPortSecurityConfig: reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif
}

 
void    SWSecurityOptionConfig(int *sourceIntrusion, int *sourceViolation)
{
    word value, protOptVal = 0;
    int  i;

    for (i = 0; i < SWI_SOURCE_VIOLATE_MAXOPT; i++) {

        if (sourceViolation[i])
            protOptVal |= (1 << (i + SWI_SOURCE_VIOLATE_OFFSET));    
    }
   
    for (i = 0; i < SWI_SOURCE_INTRUDE_MAXOPT; i++) {

        if (sourceIntrusion[i])
            protOptVal |= (1 << (i + SWI_SOURCE_INTRUDE_OFFSET));    
    }

    ifr.regAddr = SWI_SYSTEM_CTRLREG1;
    value = SWI_ioctl(RegReadMode, &ifr) & (~ SWI_INTRUDE_VIOLATE_BIT); // SWI_IOC_READEEPROM or SWI_IOC_READSMI
    ifr.regVal = (dword)(value | protOptVal);
    SWI_ioctl(RegWriteMode, &ifr); // SWI_IOC_WRITEEEPROM or SWI_IOC_WRITESMI

#ifdef  DBG
    printf("SWSecurityOptionConfig: reg[%#x]=%#lx\n", ifr.regAddr, ifr.regVal);
#endif
}


int SWLearnTableRead(int accessControl, word *portMap, int *fidVal, byte *macAddr, word *entryStatus, word *infoCtrlAge)
{
    int i, j;
    word value, accessCode, commandCode, portMapVal = 0;
    word accessTable[]= {SWI_ACCESS_SEARCH_EMPTYMAC, SWI_ACCESS_SEARCH_OUTPORT, SWI_ACCESS_SEARCH_FWDGRP,
                         SWI_ACCESS_SEARCH_MACADDR, SWI_ACCESS_SEARCH_FWGPMAC, SWI_ACCESS_SEARCH_MACOUTPT,
                         SWI_ACCESS_SEARCH_FWGOUTPT, SWI_ACCESS_SEARCH_FWMACOUT};

   for (i = 0; i < SWI_MAX_PORT_NUMBER; i++) {

        if (portMap[i])
            portMapVal |= (1 << i);    
    }

    ifr.regAddr = SWI_ADDRTBL_STATREG5;
    value = SWI_ioctl(SWI_IOC_READSMI, &ifr);

    for (i = 0; i < 100; i++) {

        if (!(value & SWI_LRNTABL_ACCESS_BUSY)) 

            break;
        else { 

            delay(5);
            value = SWI_ioctl(SWI_IOC_READSMI, &ifr);
        }
    }
    if (i == 100) {

        return(SWI_COMMAND_ENTRY_BUSY);
    }

    commandCode = SWI_COMMAND_SEARCH_MAC;
    accessCode = accessTable[accessControl];

    if (accessControl == 1) {

        for (i = 0; i < SWI_MACADDR_LENGTH; i++)
            macAddr[i] = 0;
    }

#ifdef  DBG
    printf("SWLearnTableRead: Set >> ");
#endif

    accessCode |= (commandCode << SWI_LRNTBL_COMMAND_OFFSET);

    for (i = 0, j = 5; i < 3; i++) {