ifx_swdrv.h

Switch,Ic,driver,英飛凌6996m驅動程式,包括bandwidth-control以及basic-control功能

  
    udelay(ADM_SW_MDC_DOWN_DELAY);
  
    /* set MDIO pin to output mode */
    ifx_mdio_mode(ADM_SW_MDIO_OUTPUT);
  
    /* start write data (D31~D0), mod - 06/29/05,bolo */ 
    op = ADM_SW_BIT_MASK_16; // Set ADM_SW_BIT_MASK_32 when 32-bit SMI access is configured on the board
    while (op)
    {
        if (op & dat)
            ifx_mdio_hi();
        else 
            ifx_mdio_lo();
    
        ifx_sw_mdc_pulse();
        op >>= 1;
    }
  
    /* set MDIO to output mode */
    ifx_mdio_mode(ADM_SW_MDIO_OUTPUT);
  
    /* dummy clock */
    op = ADM_SW_BIT_MASK_4;
    ifx_mdio_lo();
    while(op)
    {
        ifx_sw_mdc_pulse();
        op >>= 1;
    }
  
    ifx_mdc_lo();
    ifx_mdio_lo();  
    ifx_mdcs_hi();

    return 0;
}

#ifdef  EEPROM // add - 06/29/05,bolo
/* 
  enable eeprom write
  For ATC 93C66 type EEPROM; accessing ADM6996 internal EEPROM type registers
*/
static void ifx_sw_eeprom_write_enable(void)
{
    unsigned int op;
  
    ifx_mdcs_lo();
    ifx_mdc_lo();
    ifx_mdio_hi();
    udelay(ADM_SW_CS_DELAY);

    /* enable chip select */
    ifx_mdcs_hi();
    udelay(ADM_SW_CS_DELAY);

    /* start bit */
    ifx_mdio_hi();
    ifx_sw_mdc_pulse();
  
    /* eeprom write enable */
    op = ADM_SW_BIT_MASK_4;
    while (op)
    {
        if (op & ADM_SW_EEPROM_WRITE_ENABLE)
            ifx_mdio_hi();
        else
            ifx_mdio_lo();
    
        ifx_sw_mdc_pulse();
        op >>= 1;
    }
  
    op = ADM_SW_BIT_MASK_1 << (EEPROM_TYPE - 3);
    while (op)
    {
        ifx_mdio_lo();    
        ifx_sw_mdc_pulse();
        op >>= 1;
    }

    /* disable chip select */
    ifx_mdcs_lo();
    udelay(ADM_SW_CS_DELAY);
    ifx_sw_mdc_pulse();
}

/* 
  disable eeprom write 
*/
static void ifx_sw_eeprom_write_disable(void)
{
    unsigned int op;
  
    ifx_mdcs_lo();
    ifx_mdc_lo();
    ifx_mdio_hi();
    udelay(ADM_SW_CS_DELAY);

    /* enable chip select */
    ifx_mdcs_hi();
    udelay(ADM_SW_CS_DELAY);
  
    /* start bit */
    ifx_mdio_hi();
    ifx_sw_mdc_pulse();

    /* eeprom write disable */
    op = ADM_SW_BIT_MASK_4;
    while (op)
    {
        if (op & ADM_SW_EEPROM_WRITE_DISABLE)
            ifx_mdio_hi();
        else
            ifx_mdio_lo();
    
        ifx_sw_mdc_pulse();
        op >>= 1;
    }
  
    op = ADM_SW_BIT_MASK_1 << (EEPROM_TYPE - 3);
    while (op)
    {
        ifx_mdio_lo();    
        ifx_sw_mdc_pulse();
        op >>= 1;
    }

    /* disable chip select */
    ifx_mdcs_lo();
    udelay(ADM_SW_CS_DELAY);
    ifx_sw_mdc_pulse();
}

/* 
  Read value from ADM6996I/M eeprom registers
*/
static int ifx_sw_readeep(unsigned int addr, unsigned int *dat)
{
    unsigned int op;
  
    ifx_gpio_init();
  
    /* Initialize EEPROM */
    ifx_mdcs_lo();
    ifx_mdc_lo();
    ifx_mdio_hi();
    udelay(ADM_SW_CS_DELAY);

    /* chip select */
    ifx_mdcs_hi();
    udelay(ADM_SW_CS_DELAY);
  
    /* issue write command */
    /* start bit */
    ifx_mdio_hi();
    ifx_sw_mdc_pulse();
  
    /* EEPROM read command */
    op = ADM_SW_BIT_MASK_2;
    while (op)
    {
        if (op & ADM_SW_EEPROM_READ)
            ifx_mdio_hi();
        else
            ifx_mdio_lo();
    
        ifx_sw_mdc_pulse();
        op >>= 1;
    }
  
    /* send address An ~ A0 */
    op = ADM_SW_BIT_MASK_1 << (EEPROM_TYPE - 1);
  
    while (op)
    {
        if (op & addr)
            ifx_mdio_hi();
        else 
            ifx_mdio_lo();
    
        ifx_sw_mdc_toggle();
        op >>= 1;
    }

    udelay(ADM_SW_MDC_DOWN_DELAY); // add - 07/08/05,bolo

    /* set MDIO pin to input mode */
    ifx_mdio_mode(ADM_SW_MDIO_INPUT);  
  
    /* start read data */
    *dat = 0;
    op = ADM_SW_BIT_MASK_16;
    while (op)
    {
        *dat <<= 1;
        ifx_mdc_hi();
        udelay(ADM_SW_MDC_UP_DELAY);  

        if (ifx_sw_mdio_readbit()) *dat |= 1;

        ifx_mdc_lo();
        udelay(ADM_SW_MDC_DOWN_DELAY);  
        op >>= 1;   
    }  

    /* set MDIO to output mode, add - 07/08/05,bolo */
    ifx_mdio_mode(ADM_SW_MDIO_OUTPUT);
  
    /* disable cs & wait 1 clock */
    ifx_mdcs_lo();
    udelay(ADM_SW_CS_DELAY);
    ifx_sw_mdc_toggle();

    return 0;
}

/* 
  Write value to ADM6996I/M eeprom registers
*/
static int ifx_sw_writeep(unsigned int addr, unsigned int dat)
{
    unsigned int op;
  
    ifx_gpio_init();
  
    /* enable write */
    ifx_sw_eeprom_write_enable();
  
    /* chip select */
    ifx_mdcs_hi();
    udelay(ADM_SW_CS_DELAY);
  
    /* issue write command */
    /* start bit */
    ifx_mdio_hi();
    ifx_sw_mdc_pulse();
  
    /* EEPROM write command */
    op = ADM_SW_BIT_MASK_2;
    while (op)
    {
        if (op & ADM_SW_EEPROM_WRITE)
            ifx_mdio_hi();
        else
            ifx_mdio_lo();
    
        ifx_sw_mdc_pulse();
        op >>= 1;
    }
  
    /* send address A7 ~ A0 */
    op = ADM_SW_BIT_MASK_1 << (EEPROM_TYPE - 1);
  
    while (op)
    {
        if (op & addr)
            ifx_mdio_hi();
        else 
            ifx_mdio_lo();
    
        ifx_sw_mdc_toggle();
        op >>= 1;
    }
  
    udelay(ADM_SW_MDC_DOWN_DELAY);
  
    /* start write data */
    op = ADM_SW_BIT_MASK_16;
    while (op)
    {
        if (op & dat)
            ifx_mdio_hi();
        else
            ifx_mdio_lo();

        ifx_sw_mdc_toggle();
        op >>= 1;   
    }
  
    /* disable cs & wait 1 clock */
    ifx_mdcs_lo();
    udelay(ADM_SW_CS_DELAY);
    ifx_sw_mdc_toggle();
  
    ifx_sw_eeprom_write_disable();
  
    return 0;
}
#endif // EEPROM

/*
  do switch PHY reset
*/	
void ifx_sw_reset(void)
{
    unsigned int RESET;  

    RESET = 0;
    udelay(RESET_DELAY);

    ifx_mdcs_lo();  // chip select 
    ifx_mdc_hi();   // for Samurai's dual-color LED
    ifx_mdio_hi();
    ifx_mdio_hi();

    RESET = 1;
    ifx_mdcs_hi();  // chip select 
    ifx_mdc_hi();   // for Samurai's dual-color LED
    ifx_mdio_hi();  // mod - 09/12/05,bolo for EEPROM auto-loaded into Samurai internal registers
    ifx_mdio_hi();        
}

/* 
  default VLAN setting
  
  port 0~3 as untag port and PVID = 1
  VLAN1: port 0~3 and port 5 (MII)
*/
static int ifx_sw_init(void)
{
    ifx_printf(("Setting default ADM6996 registers... \n"));
  
    /* MAC clone, 802.1q based VLAN */
    ifx_sw_write(ADM_SW_VLAN_MODE, 0xff30);
    /* auto MDIX, PVID=1, untag */
    ifx_sw_write(ADM_SW_PORT0_CONF, 0x840f);
    ifx_sw_write(ADM_SW_PORT1_CONF, 0x840f);
    ifx_sw_write(ADM_SW_PORT2_CONF, 0x840f);
    ifx_sw_write(ADM_SW_PORT3_CONF, 0x840f);
    /* auto MDIX, PVID=2, untag */
    ifx_sw_write(ADM_SW_PORT5_CONF, 0x880f);
    /* port 0~3 & 5 as VLAN1 */
    ifx_sw_write(ADM_SW_VLAN0_CONF+1, 0x0155);
  
    return 0;
}                                                        

#endif
/* _IFX_SWDRV_H_ */